- /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */
- if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) {
+ /*
+ * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
+ * Enable bit and prescaler
+ */
+ if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
+ is_mx6sll()) {