+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
+
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7)
+#define CCM_USB_CTRL_PHYGATE (0x1 << 8)
+/* These 3 are sun6i only, define them as 0 on sun4i */
+#define CCM_USB_CTRL_PHY0_CLK 0
+#define CCM_USB_CTRL_PHY1_CLK 0
+#define CCM_USB_CTRL_PHY2_CLK 0
+
+/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
+#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_DE_CTRL_PLL_MASK (3 << 24)
+#define CCM_DE_CTRL_PLL3 (0 << 24)
+#define CCM_DE_CTRL_PLL7 (1 << 24)
+#define CCM_DE_CTRL_PLL5P (2 << 24)
+#define CCM_DE_CTRL_RST (1 << 30)
+#define CCM_DE_CTRL_GATE (1 << 31)
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
+unsigned int clock_get_pll3(void);
+unsigned int clock_get_pll5p(void);
+unsigned int clock_get_pll6(void);
+#endif