+#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
+#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */
+#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16)
+
+#define CCM_MBUS_RESET_RESET (0x1 << 31)
+
+#define CCM_DRAM_GATE_OFFSET_DE_FE0 24
+#define CCM_DRAM_GATE_OFFSET_DE_FE1 25
+#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
+
+#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
+#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24)
+/* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */
+#define CCM_LCD_CH0_CTRL_RST 0
+#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
+
+#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_LCD_CH1_CTRL_HALF_SCLK1 0 /* no seperate sclk1 & 2 on sun6i */
+#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
+#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31)
+
+#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
+#define CCM_HDMI_CTRL_PLL3 (0 << 24)
+#define CCM_HDMI_CTRL_PLL7 (1 << 24)
+#define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
+#define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
+#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
+#define CCM_HDMI_CTRL_GATE (0x1 << 31)
+
+#if defined(CONFIG_MACH_SUN50I)
+#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */
+#elif defined(CONFIG_MACH_SUN8I)
+#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
+#else
+#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
+#endif
+#define MBUS_CLK_GATE (0x1 << 31)
+
+#define CCM_PLL5_PATTERN 0xd1303333
+#define CCM_PLL11_PATTERN 0xf5860000
+
+/* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_GMAC 17
+#define AHB_RESET_OFFSET_MCTL 14