-
- /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
- uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */
- uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+ u32 _rsv32[4]; /* 0x560-0x56c */
+ u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
+ u32 _rsv32_1[7]; /* 0x574-58c */
+ struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
+ u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
+
+ /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+ uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
+ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+ /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+ uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
+ /*
+ * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+ * two later if PLLA1 is needed, but for now this is cleaner.
+ */
+ uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */