+ /* The following fields are in Tegra124 and later only */
+ uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */
+ uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */
+ uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */
+ uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */
+ uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
+ uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */
+ uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */
+ uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */
+ uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */
+ uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */
+ uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */
+ uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */
+ uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */
+ uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */
+ uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */
+ uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */
+ uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */
+ uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */
+ uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */
+ uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */
+ uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */
+ uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */
+ uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */
+ uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */
+ uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */
+ uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */
+ uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */
+ uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */
+
+ uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */
+ uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */
+ uint pmc_reserved0; /* _RESERVED, offset 1D8 */
+ uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
+ uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */
+ uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */
+ uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */
+ uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
+ uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
+ uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */
+ uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
+ uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
+
+ uint pmc_todo_0[9]; /* offset 200-220 */
+ uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */
+ uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */
+ uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */
+ uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */
+ uint pmc_scratch45;
+ uint pmc_scratch46;
+ uint pmc_scratch47;
+ uint pmc_scratch48;
+ uint pmc_scratch49;
+ uint pmc_scratch50;
+ uint pmc_scratch51;
+ uint pmc_scratch52;
+ uint pmc_scratch53;
+ uint pmc_scratch54;
+ uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */
+ uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */
+ uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */
+ uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */
+ uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */
+ uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */
+ uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */
+ uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
+ uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */
+ uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */
+ uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */
+ uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */
+ uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */
+ uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */
+ uint pmc_secure_scratch9;
+ uint pmc_secure_scratch10;
+ uint pmc_secure_scratch11;
+ uint pmc_secure_scratch12;
+ uint pmc_secure_scratch13;
+ uint pmc_secure_scratch14;
+ uint pmc_secure_scratch15;
+ uint pmc_secure_scratch16;
+ uint pmc_secure_scratch17;
+ uint pmc_secure_scratch18;
+ uint pmc_secure_scratch19;
+ uint pmc_secure_scratch20;
+ uint pmc_secure_scratch21;
+ uint pmc_secure_scratch22;
+ uint pmc_secure_scratch23;
+ uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */
+ uint pmc_secure_scratch25;
+ uint pmc_secure_scratch26;
+ uint pmc_secure_scratch27;
+ uint pmc_secure_scratch28;
+ uint pmc_secure_scratch29;
+ uint pmc_secure_scratch30;
+ uint pmc_secure_scratch31;
+ uint pmc_secure_scratch32;
+ uint pmc_secure_scratch33;
+ uint pmc_secure_scratch34;
+ uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */
+
+ uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */
+ uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */
+ uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */
+ uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */
+ uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */
+ uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */
+ uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */
+
+ uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */
+ uint pmc_scratch57;
+ uint pmc_scratch58;
+ uint pmc_scratch59;
+ uint pmc_scratch60;
+ uint pmc_scratch61;
+ uint pmc_scratch62;
+ uint pmc_scratch63;
+ uint pmc_scratch64;
+ uint pmc_scratch65;
+ uint pmc_scratch66;
+ uint pmc_scratch67;
+ uint pmc_scratch68;
+ uint pmc_scratch69;
+ uint pmc_scratch70;
+ uint pmc_scratch71;
+ uint pmc_scratch72;
+ uint pmc_scratch73;
+ uint pmc_scratch74;
+ uint pmc_scratch75;
+ uint pmc_scratch76;
+ uint pmc_scratch77;
+ uint pmc_scratch78;
+ uint pmc_scratch79;
+ uint pmc_scratch80;
+ uint pmc_scratch81;
+ uint pmc_scratch82;
+ uint pmc_scratch83;
+ uint pmc_scratch84;
+ uint pmc_scratch85;
+ uint pmc_scratch86;
+ uint pmc_scratch87;
+ uint pmc_scratch88;
+ uint pmc_scratch89;
+ uint pmc_scratch90;
+ uint pmc_scratch91;
+ uint pmc_scratch92;
+ uint pmc_scratch93;
+ uint pmc_scratch94;
+ uint pmc_scratch95;
+ uint pmc_scratch96;
+ uint pmc_scratch97;
+ uint pmc_scratch98;
+ uint pmc_scratch99;
+ uint pmc_scratch100;
+ uint pmc_scratch101;
+ uint pmc_scratch102;
+ uint pmc_scratch103;
+ uint pmc_scratch104;
+ uint pmc_scratch105;
+ uint pmc_scratch106;
+ uint pmc_scratch107;
+ uint pmc_scratch108;
+ uint pmc_scratch109;
+ uint pmc_scratch110;
+ uint pmc_scratch111;
+ uint pmc_scratch112;
+ uint pmc_scratch113;
+ uint pmc_scratch114;
+ uint pmc_scratch115;
+ uint pmc_scratch116;
+ uint pmc_scratch117;
+ uint pmc_scratch118;
+ uint pmc_scratch119;
+ uint pmc_scratch1_eco; /* offset 700 */