+
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1 0x410FC091
+#define MIDR_CORTEX_A9_R1P2 0x411FC092
+#define MIDR_CORTEX_A9_R1P3 0x411FC093
+#define MIDR_CORTEX_A9_R2P10 0x412FC09A
+
+/* Cortex-A15 revisions */
+#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
+#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
+
+/* Cortex-A7 revisions */
+#define MIDR_CORTEX_A7_R0P0 0x410FC070
+
+#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
+
+/* ID_PFR1 feature fields */
+#define CPUID_ARM_SEC_SHIFT 4
+#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT)
+#define CPUID_ARM_VIRT_SHIFT 12
+#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT)
+#define CPUID_ARM_GENTIMER_SHIFT 16
+#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT)
+
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK 0xFFFF8000