+#ifdef CONFIG_ARMV7_LPAE
+ /* Set up 4 PTE entries pointing to our 4 1GB page tables */
+ for (i = 0; i < 4; i++) {
+ u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
+ u64 tpt = gd->arch.tlb_addr + (4096 * i);
+ page_table[i] = tpt | TTB_PAGETABLE;
+ }
+
+ reg = TTBCR_EAE;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+ reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
+#else
+ reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
+#endif
+
+ if (is_hyp()) {
+ /* Set HCTR to enable LPAE */
+ asm volatile("mcr p15, 4, %0, c2, c0, 2"
+ : : "r" (reg) : "memory");
+ /* Set HTTBR0 */
+ asm volatile("mcrr p15, 4, %0, %1, c2"
+ :
+ : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
+ : "memory");
+ /* Set HMAIR */
+ asm volatile("mcr p15, 4, %0, c10, c2, 0"
+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ } else {
+ /* Set TTBCR to enable LPAE */
+ asm volatile("mcr p15, 0, %0, c2, c0, 2"
+ : : "r" (reg) : "memory");
+ /* Set 64-bit TTBR0 */
+ asm volatile("mcrr p15, 0, %0, %1, c2"
+ :
+ : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
+ : "memory");
+ /* Set MAIR */
+ asm volatile("mcr p15, 0, %0, c10, c2, 0"
+ : : "r" (MEMORY_ATTRIBUTES) : "memory");
+ }
+#elif defined(CONFIG_CPU_V7)
+ /* Set TTBR0 */
+ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+ reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
+#else
+ reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
+#endif
+ asm volatile("mcr p15, 0, %0, c2, c0, 0"
+ : : "r" (reg) : "memory");
+#else