+void set_section_dcache(int section, enum dcache_option option)
+{
+#ifdef CONFIG_ARMV7_LPAE
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+ /* Need to set the access flag to not fault */
+ u64 value = TTB_SECT_AP | TTB_SECT_AF;
+#else
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
+ u32 value = TTB_SECT_AP;
+#endif
+
+ /* Add the page offset */
+ value |= ((u32)section << MMU_SECTION_SHIFT);
+
+ /* Add caching bits */
+ value |= option;
+
+ /* Set PTE */
+ page_table[section] = value;
+}
+
+__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+ debug("%s: Warning: not implemented\n", __func__);
+}
+
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ enum dcache_option option)
+{
+#ifdef CONFIG_ARMV7_LPAE
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+#else
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
+#endif
+ unsigned long startpt, stoppt;
+ unsigned long upto, end;
+
+ end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+ start = start >> MMU_SECTION_SHIFT;
+#ifdef CONFIG_ARMV7_LPAE
+ debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
+ option);
+#else
+ debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
+ option);
+#endif
+ for (upto = start; upto < end; upto++)
+ set_section_dcache(upto, option);
+
+ /*
+ * Make sure range is cache line aligned
+ * Only CPU maintains page tables, hence it is safe to always
+ * flush complete cache lines...
+ */
+
+ startpt = (unsigned long)&page_table[start];
+ startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ stoppt = (unsigned long)&page_table[end];
+ stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+ mmu_page_table_flush(startpt, stoppt);
+}
+
+__weak void dram_bank_mmu_setup(int bank)