-
-/* Change the reset state for EMAC 0 and EMAC 1 */
-void socfpga_emac_reset(int enable)
-{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- if (enable) {
- setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
- setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
- } else {
-#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
-#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
-#endif
- }
-}
-
-/* SPI Master enable (its held in reset by the preloader) */
-void socfpga_spim_enable(void)
-{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
- (1 << RSTMGR_PERMODRST_SPIM1_LSB));
-}
-
-/* Bring UART0 out of reset. */
-void socfpga_uart0_enable(void)
-{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB);
-}
-
-/* Bring SDRAM controller out of reset. */
-void socfpga_sdram_enable(void)
-{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB);
-}
-
-/* Bring OSC1 timer out of reset. */
-void socfpga_osc1timer_enable(void)
-{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
-}