-#ifdef CONFIG_UNIPHIER_SMP
- /*
- * ACTLR (Auxiliary Control Register) for Cortex-A9
- * bit[9] Parity on
- * bit[8] Alloc in one way
- * bit[7] EXCL (Exclusive cache bit)
- * bit[6] SMP
- * bit[3] Write full line of zeros mode
- * bit[2] L1 Prefetch enable
- * bit[1] L2 prefetch enable
- * bit[0] FW (Cache and TLB maintenance broadcast)
- */
- mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
- orr r0, r0, #0x41 @ enable SMP, FW bit
- mcr p15, 0, r0, c1, c0, 1
-
- /* branch by CPU ID */
- mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
- and r0, r0, #0x3
- cmp r0, #0x0
- beq primary_cpu
- ldr r1, =ROM_BOOT_ROMRSV2
- mov r0, #0
- str r0, [r1]
-0: wfe
- ldr r0, [r1]
- cmp r0, #0
- beq 0b
- bx r0 @ r0: entry point of U-Boot main for the secondary CPU
-primary_cpu:
- ldr r1, =ROM_BOOT_ROMRSV2
- ldr r0, =_start @ entry for the secondary CPU
- str r0, [r1]
- ldr r0, [r1] @ make sure str is complete before sev
- sev @ kick the sedoncary CPU
- mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
- bfc r1, #0, #13 @ clear bit 12-0
- mov r0, #-1
- str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
- mov r0, #1 @ SCU enable
- str r0, [r1, #SCU_CTRL] @ SCU Control Register
-#endif
-