+
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+ debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+ sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+ if (sel == 0x01 || sel == 0x02) {
+ for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+ /* STEP 1 */
+ /* Read factory pre-set SerDes calibration values
+ * from fuse block(SFP scratch register-sfp_spfr0)
+ */
+ switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+ case SRDS_PLLCR0_FRATE_SEL_3_0:
+ case SRDS_PLLCR0_FRATE_SEL_3_072:
+ debug("A007186: 3.0/3.072 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_125:
+ debug("A007186: 3.125 protocol rate\n");
+ bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_75:
+ debug("A007186: 3.75 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ default:
+ continue;
+ }
+
+ /* STEP 2 */
+ /* Write SRDSxPLLnCR1[11:16] = FC
+ * Write SRDSxPLLnCR1[2] = BC
+ */
+ pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+ pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
+ ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+ /* Write SRDSxPLLnCR0[24:26] = DC
+ */
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+ debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
+ pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+ /* Write SRDSxPLLnCR1[3] = 1
+ * Write SRDSxPLLnCR1[6] = 1
+ */
+ pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+ pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+
+ /* STEP 3 */
+ /* Read the status Registers */
+ /* Verify SRDSxPLLnSR2[8] = BC */
+ pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+ debug("A007186: pll_num=%x pllsr2=%x\n",
+ pll_num, pll_sr2);
+ bc_status = (pll_sr2 >> 23) & BC_MASK;
+ if (bc_status != bc)
+ debug("BC mismatch\n");
+ fc_status = (pll_sr2 >> 16) & FC_MASK;
+ if (fc_status != fc)
+ debug("FC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
+ 0x02000000);
+ pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+ dc_status = (pll_sr2 >> 17) & DC_MASK;
+ if (dc_status != dc)
+ debug("DC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
+ 0xfdffffff);
+
+ /* STEP 4 */
+ /* Wait 750us to verify the PLL is locked
+ * by checking SRDSxPLLnCR0[8] = 1.
+ */
+ udelay(750);
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+
+ if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+ printf("A007186 Serdes PLL not locked\n");
+ else
+ debug("A007186 Serdes PLL locked\n");
+ }