x86: Add LAPIC setup code

[u-boot] / arch / x86 / Kconfig

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index aa7cf779910edca925392e630622e4cde6cced95..6e29868f5f8f90fcb03e115e6375e02ab90a6997 100644 (file)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -34,6 +34,33 @@ config TARGET_CHROMEBOOK_LINK
 
 endchoice
 
 
 endchoice
 

+config RAMBASE
+       hex
+       default 0x100000
+
+config RAMTOP
+       hex
+       default 0x200000
+
+config XIP_ROM_SIZE
+       hex
+       default 0x10000
+
+config CPU_ADDR_BITS
+       int
+       default 36
+
+config HPET_ADDRESS
+       hex
+       default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
+
+config SMM_TSEG
+       bool
+       default n
+
+config SMM_TSEG_SIZE
+       hex
+

 config ROM_SIZE
        hex
        default 0x800000
 config ROM_SIZE
        hex
        default 0x800000


@@ -47,9 +74,18 @@ config HAVE_INTEL_ME
          SPI flash format. You will need to supply the me.bin file in
          your board directory.
 
          SPI flash format. You will need to supply the me.bin file in
          your board directory.
 

+config X86_RAMTEST
+       bool "Perform a simple RAM test after SDRAM initialisation"
+       help
+         If there is something wrong with SDRAM then the platform will
+         often crash within U-Boot or the kernel. This option enables a
+         very simple RAM test that quickly checks whether the SDRAM seems
+         to work correctly. It is not exhaustive but can save time by
+         detecting obvious failures.
+

 source "arch/x86/cpu/ivybridge/Kconfig"
 
 source "arch/x86/cpu/ivybridge/Kconfig"
 

-source "board/chromebook-x86/coreboot/Kconfig"
+source "board/coreboot/coreboot/Kconfig"

 
 source "board/google/chromebook_link/Kconfig"
 
 
 source "board/google/chromebook_link/Kconfig"