-static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
-{
- /* Enable port 80 POST on LPC */
- pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
- clrbits_le32(RCB_REG(GCS), 4);
-}
-
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
-{
- u8 reg8;
-
- pci_hose_read_config_byte(hose, dev, 0xdc, ®8);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
-}
-
-static void set_var_mtrr(
- unsigned reg, unsigned base, unsigned size, unsigned type)
-
-{
- /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
- /* FIXME: It only support 4G less range */
- wrmsr(MTRRphysBase_MSR(reg), base | type, 0);
- wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid,
- (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1);
-}
-
-static void enable_rom_caching(void)
-{
- disable_caches();
- set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT);
- enable_caches();
-
- /* Enable Variable MTRRs */
- wrmsr(MTRRdefType_MSR, 0x800, 0);
-}
-