+#define PCH_EHCI0_TEMP_BAR0 0xe8000000
+#define PCH_EHCI1_TEMP_BAR0 0xe8000400
+#define PCH_XHCI_TEMP_BAR0 0xe8001000
+
+/*
+ * Setup USB controller MMIO BAR to prevent the reference code from
+ * resetting the controller.
+ *
+ * The BAR will be re-assigned during device enumeration so these are only
+ * temporary.
+ *
+ * This is used to speed up the resume path.
+ */
+static void enable_usb_bar(struct udevice *bus)
+{
+ pci_dev_t usb0 = PCH_EHCI1_DEV;
+ pci_dev_t usb1 = PCH_EHCI2_DEV;
+ pci_dev_t usb3 = PCH_XHCI_DEV;
+ ulong cmd;
+
+ /* USB Controller 1 */
+ pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
+ PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
+ pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
+
+ /* USB Controller 2 */
+ pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
+ PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
+ pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
+
+ /* USB3 Controller 1 */
+ pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
+ PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
+ pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
+}
+
+int checkcpu(void)