- cma_mb_reg_write(&mbsp->ser_ier, 0x00); /* turn off interrupts */
- cma_mb_reg_write(&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB)*/
- cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff);
- cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff);
- cma_mb_reg_write(&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */
- cma_mb_reg_write(&mbsp->ser_mcr, 0x03); /* RTS/DTR */
- cma_mb_reg_write(&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */
+ cma_mb_reg_write (&mbsp->ser_ier, 0x00); /* turn off interrupts */
+ cma_mb_reg_write (&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB) */
+ cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
+ cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
+ cma_mb_reg_write (&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */
+ cma_mb_reg_write (&mbsp->ser_mcr, 0x03); /* RTS/DTR */
+ cma_mb_reg_write (&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */