-
-#else /* NEW_SDRAM_INIT */
-
- /* configure the MEMCLKCFG register */
- ldr r1, =MEMCLKCFG
- ldr r2, =0x00010001
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set CSADRCFG[0] to data flash SRAM mode */
- ldr r1, =CSADRCFG0
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set CSADRCFG[1] to data flash SRAM mode */
- ldr r1, =CSADRCFG1
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set MSC 0 register for SRAM memory */
- ldr r1, =MSC0
- ldr r2, =0x11191119
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set CSADRCFG[2] to data flash SRAM mode */
- ldr r1, =CSADRCFG2
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set CSADRCFG[3] to VLIO mode */
- ldr r1, =CSADRCFG3
- ldr r2, =0x0032080B
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set MSC 1 register for VLIO memory */
- ldr r1, =MSC1
- ldr r2, =0x123C1119
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
-#if 0
- /* This does not work in Zylonite. -SC */
- ldr r0, =0x15fffff0
- ldr r1, =0xb10b
- str r1, [r0]
- str r1, [r0, #4]
-#endif
-
- /* Configure ACCR Register */
- ldr r0, =ACCR @ ACCR
- ldr r1, =0x0180b108
- str r1, [r0]
- ldr r1, [r0]
-
- /* Configure MDCNFG Register */
- ldr r0, =MDCNFG @ MDCNFG
- ldr r1, =0x403
- str r1, [r0]
- ldr r1, [r0]
-
- /* Perform Resistive Compensation by configuring RCOMP register */
- ldr r1, =RCOMP @ RCOMP
- ldr r2, =0x000000ff
- str r2, [r1]
- ldr r2, [r1]
-
- /* Configure MDMRS Register for SDCS0 */
- ldr r1, =MDMRS @ MDMRS
- ldr r2, =0x60000023
- ldr r3, [r1]
- orr r2, r2, r3
- str r2, [r1]
- ldr r2, [r1]
-
- /* Configure MDMRS Register for SDCS1 */
- ldr r1, =MDMRS @ MDMRS
- ldr r2, =0xa0000023
- ldr r3, [r1]
- orr r2, r2, r3
- str r2, [r1]
- ldr r2, [r1]
-
- /* Configure MDREFR */
- ldr r1, =MDREFR @ MDREFR
- ldr r2, =0x00000006
- str r2, [r1]
- ldr r2, [r1]
-
- /* Configure EMPI */
- ldr r1, =EMPI @ EMPI
- ldr r2, =0x80000000
- str r2, [r1]
- ldr r2, [r1]
-
- /* Hardware DDR Read-Strobe Delay Calibration */
- ldr r0, =DDR_HCAL @ DDR_HCAL
- ldr r1, =0x803ffc07 @ the offset is correct? -SC
- str r1, [r0]
- wait #5
- ldr r1, [r0]
-
- /* Here we assume the hardware calibration alwasy be successful. -SC */
- /* Set DMCEN bit in MDCNFG Register */
- ldr r0, =MDCNFG @ MDCNFG
- ldr r1, [r0]
- orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
- str r1, [r0]
-
-#endif /* NEW_SDRAM_INIT */
-
-#ifndef CFG_SKIP_DRAM_SCRUB