- case DDR_CL_2:
- if (tmp == 1) /* Sync*/
- {
- tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk*/
- tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4*/
- DP(printf("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
- }
- else /* Not sync. */
- {
- tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk*/
- tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4*/
- DP(printf("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
- }
- break;
-
- case DDR_CL_1_5:
- if (tmp == 1) /* Sync*/
- {
- tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk*/
- tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4*/
- DP(printf("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
- }
- else /* not sync*/
- {
- tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk*/
- tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4*/
- DP(printf("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",tmp_sdram_mode, tmp_dunit_control_low ));
- }
- break;
+ case DDR:
+ DP (printf ("### SET-CL for DDR-RAM\n"));
+
+ switch (info->maxClSupported_DDR) {
+ case DDR_CL_3:
+ tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */
+ tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
+ DP (printf
+ ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low));
+ break;
+
+ case DDR_CL_2_5:
+ if (tmp == 1) { /* clocks sync */
+ tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */
+ tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
+ DP (printf
+ ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low));
+ } else { /* clk sync. bypassed */
+
+ tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
+ tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */
+ DP (printf
+ ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low));
+ }
+ break;
+
+ case DDR_CL_2:
+ if (tmp == 1) { /* Sync */
+ tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */
+ tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
+ DP (printf
+ ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low));
+ } else { /* Not sync. */
+
+ tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */
+ tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
+ DP (printf
+ ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low));
+ }
+ break;
+
+ case DDR_CL_1_5:
+ if (tmp == 1) { /* Sync */
+ tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */
+ tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
+ DP (printf
+ ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low));
+ } else { /* not sync */
+
+ tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */
+ tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */
+ DP (printf
+ ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+ tmp_sdram_mode, tmp_dunit_control_low));
+ }
+ break;