+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
+
+ memctl->memc_mptpr = MPTPR_2BK_4K;
+ memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */
+
+ /* map CS 4 */
+ memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
+ memctl->memc_br4 = SDRAM_BR4VALUE | base;
+
+ /* Perform SDRAM initilization */
+# ifdef UPM_NOP_ADDR /* not currently in UPM table */
+ /* step 1: nop */
+ memctl->memc_mar = 0x00000000;
+ memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+ MCR_MLCF(0) | UPM_NOP_ADDR;
+# endif
+
+ /* step 2: delay */
+ udelay(200);
+
+# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
+ /* step 3: precharge */
+ memctl->memc_mar = 0x00000000;
+ memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+ MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
+# endif
+
+ /* step 4: refresh */
+ memctl->memc_mar = 0x00000000;
+ memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+ MCR_MLCF(2) | UPM_REFRESH_ADDR;
+
+ /*
+ * note: for some reason, the UPM values we are using include
+ * precharge with MRS
+ */
+
+ /* step 5: mrs */
+ memctl->memc_mar = 0x00000088;
+ memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+ MCR_MLCF(1) | UPM_MRS_ADDR;
+
+# ifdef UPM_NOP_ADDR
+ memctl->memc_mar = 0x00000000;
+ memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+ MCR_MLCF(0) | UPM_NOP_ADDR;
+# endif
+ /*
+ * Enable refresh
+ */
+
+ memctl->memc_mbmr |= MBMR_PTBE;
+ return 0;
+}
+#endif /* !SDRAM_ALT_INIT_SEQUENCE */
+
+/* ------------------------------------------------------------------------- */
+
+static void _sdramdisable(void)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;