+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ void (*second_uboot)(void);
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ get_clocks();
+
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ preloader_console_init();
+
+ dram_init();
+
+ /* Allow OCRAM access permission as R/W */
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+ enable_layerscape_ns_access();
+#endif
+
+ /*
+ * if it is woken up from deep sleep, then jump to second
+ * stage uboot and continue executing without recopying
+ * it from SD since it has already been reserved in memeory
+ * in last boot.
+ */
+ if (is_warm_boot()) {
+ second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
+ second_uboot();
+ }
+
+ board_init_r(NULL, 0);
+}
+#endif
+
+#ifdef CONFIG_DEEP_SLEEP
+/* program the regulator (MC34VR500) to support deep sleep */
+void ls1twr_program_regulator(void)
+{
+ unsigned int i2c_bus;
+ u8 i2c_device_id;
+
+#define LS1TWR_I2C_BUS_MC34VR500 1
+#define MC34VR500_ADDR 0x8
+#define MC34VR500_DEVICEID 0x4
+#define MC34VR500_DEVICEID_MASK 0x0f
+
+ i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
+ i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
+ MC34VR500_DEVICEID_MASK;
+ if (i2c_device_id != MC34VR500_DEVICEID) {
+ printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
+ return;
+ }
+
+ i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
+ i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
+ i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
+ i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
+ i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
+
+ i2c_set_bus_num(i2c_bus);
+}
+#endif
+