+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
+
+ printf("SERDES Reference : 0x%X\n", srds_s1);
+
+ /* select SGMII*/
+ if (srds_s1 == 0x86)
+ CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+ MISC_CTL_SG_SEL);
+
+ /* select SGMII and Aurora*/
+ if (srds_s1 == 0x8E)
+ CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+ MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
+
+#if defined(CONFIG_T1040D4RDB)
+ if (hwconfig("qe-tdm")) {
+ CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
+ MISC_MUX_QE_TDM);
+ printf("QECSR : 0x%02x, mux to qe-tdm\n",
+ CPLD_READ(sfp_ctl_status));
+ }
+ /* Mask all CPLD interrupt sources, except QSGMII interrupts */
+ if (CPLD_READ(sw_ver) < 0x03) {
+ debug("CPLD SW version 0x%02x doesn't support int_mask\n",
+ CPLD_READ(sw_ver));
+ } else {
+ CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
+ ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
+ }
+#endif
+