+ int i;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT1:
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ break;
+ case EMI1_SLOT2:
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ break;
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case EMI1_SLOT4:
+ fdt_status_okay_by_alias(fdt, "emi1_slot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ /* check if it's XFI interface for 10g */
+ if ((prtcl2 == 56) || (prtcl2 == 57)) {
+ fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
+ break;
+ }
+ switch (i) {
+ case FM1_10GEC1:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
+ break;
+ case FM1_10GEC2:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
+ break;
+ case FM2_10GEC1:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
+ break;
+ case FM2_10GEC2:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void initialize_qsgmiiphy_fix(void)
+{
+ int i;
+ unsigned short reg;
+
+ for (i = 1; i <= 4; i++) {
+ /*
+ * Try to read if a SGMII card is used, we do it slot by slot.
+ * if a SGMII PHY address is valid on a slot, then we mark
+ * all ports on the slot, then fix the PHY address for the
+ * marked port when doing dtb fixup.
+ */
+ if (miiphy_read(mdio_names[i],
+ SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
+ debug("Slot%d PHY ID register 2 read failed\n", i);
+ continue;
+ }
+
+ debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
+
+ if (reg == 0xFFFF) {
+ /* No physical device present at this address */
+ continue;
+ }
+
+ switch (i) {
+ case 1:
+ qsgmiiphy_fix[FM1_DTSEC5] = 1;
+ qsgmiiphy_fix[FM1_DTSEC6] = 1;
+ qsgmiiphy_fix[FM1_DTSEC9] = 1;
+ qsgmiiphy_fix[FM1_DTSEC10] = 1;
+ slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 2:
+ qsgmiiphy_fix[FM1_DTSEC1] = 1;
+ qsgmiiphy_fix[FM1_DTSEC2] = 1;
+ qsgmiiphy_fix[FM1_DTSEC3] = 1;
+ qsgmiiphy_fix[FM1_DTSEC4] = 1;
+ slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 3:
+ qsgmiiphy_fix[FM2_DTSEC5] = 1;
+ qsgmiiphy_fix[FM2_DTSEC6] = 1;
+ qsgmiiphy_fix[FM2_DTSEC9] = 1;
+ qsgmiiphy_fix[FM2_DTSEC10] = 1;
+ slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 4:
+ qsgmiiphy_fix[FM2_DTSEC1] = 1;
+ qsgmiiphy_fix[FM2_DTSEC2] = 1;
+ qsgmiiphy_fix[FM2_DTSEC3] = 1;
+ qsgmiiphy_fix[FM2_DTSEC4] = 1;
+ slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ default:
+ break;
+ }
+ }