+static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x0048004A,
+ .p0_mpwldectrl1 = 0x003F004A,
+ .p1_mpwldectrl0 = 0x001E0028,
+ .p1_mpwldectrl1 = 0x002C0043,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x02250219,
+ .p0_mpdgctrl1 = 0x01790202,
+ .p1_mpdgctrl0 = 0x02080208,
+ .p1_mpdgctrl1 = 0x016C0175,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x4A4C4D4C,
+ .p1_mprddlctl = 0x494C4A48,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x403F3437,
+ .p1_mpwrdlctl = 0x383A3930,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x001F003F,
+ .p0_mpwldectrl1 = 0x001F001F,
+ .p1_mpwldectrl0 = 0x001F004E,
+ .p1_mpwldectrl1 = 0x0059001F,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42220225,
+ .p0_mpdgctrl1 = 0x0213021F,
+ .p1_mpdgctrl0 = 0x022C0242,
+ .p1_mpdgctrl1 = 0x022C0244,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x474A4C4A,
+ .p1_mprddlctl = 0x48494C45,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x3F3F3F36,
+ .p1_mpwrdlctl = 0x3F36363F,
+};
+
+static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x002A0025,
+ .p0_mpwldectrl1 = 0x003A002A,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43430356,
+ .p0_mpdgctrl1 = 0x033C0335,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x4B373F42,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x303E3C36,
+};
+
+static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00230020,
+ .p0_mpwldectrl1 = 0x002F002A,
+ .p1_mpwldectrl0 = 0x001D0027,
+ .p1_mpwldectrl1 = 0x00100023,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x03250339,
+ .p0_mpdgctrl1 = 0x031C0316,
+ .p1_mpdgctrl0 = 0x03210331,
+ .p1_mpdgctrl1 = 0x031C025A,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x40373C40,
+ .p1_mprddlctl = 0x3A373646,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x2E353933,
+ .p1_mpwrdlctl = 0x3C2F3F35,
+};
+