- /*
- * Map controller bank 5 for SHARC
- */
- memctl->memc_or5 = CFG_OR5;
- memctl->memc_br5 = CFG_BR5;
-
- memctl->memc_mamr = 0x00001000;
-
- /*
- * Configure UPMB for SDRAM
- */
- upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
-
- memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
-
- udelay(200);
- memctl->memc_mcr = 0x80806105; /* precharge */
- udelay(1);
- memctl->memc_mcr = 0x80806106; /* load mode register */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
-
- memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
- size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
-
- return (size_b0);
+ /*
+ * Map controller bank 5 for SHARC
+ */
+ memctl->memc_or5 = CFG_OR5;
+ memctl->memc_br5 = CFG_BR5;
+
+ memctl->memc_mamr = 0x00001000;
+
+ /*
+ * Configure UPMB for SDRAM
+ */
+ upmconfig (UPMB, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
+
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+
+ memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
+
+ udelay (200);
+ memctl->memc_mcr = 0x80806105; /* precharge */
+ udelay (1);
+ memctl->memc_mcr = 0x80806106; /* load mode register */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+
+ memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
+ size_b0 =
+ dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
+ SDRAM_MAX_SIZE);
+
+ memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+
+ return (size_b0);