-#define BOARD_BW 0 /* 16Bit */
-#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
-
-
-/* UART0 CS2 */
-#define UART0_BME 0 /* Burst disable */
-#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
-#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define UART0_OEN 1 /* Cycles from CS low to OE low */
-#define UART0_WBN 1 /* Cycles from CS low to WE low */
-#define UART0_WBF 1 /* Cycles from WE high to CS high */
-#define UART0_TH 2 /* Number of hold cycles after transfer */
-#define UART0_RE 0 /* Ready disabled */
-#define UART0_SOR 1 /* Sample on Ready disabled */
-#define UART0_BEM 0 /* Byte Write only active on Write cycles */
-#define UART0_PEN 0 /* Parity disable */
-#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
- (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define UART0_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define UART0_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define UART0_BW 0 /* 8Bit */
-#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-/* UART1 CS3 */
-#define UART1_AP UART0_AP /* same timing as UART0 */
-#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-