-
-#if !defined(CONFIG_SPD_EEPROM)
- dram_size = fixed_hcu4_sdram();
-#else
-#ifdef DO_UGLY_SDRAM_WORKAROUND
- /* Workaround if you have no working I2C-EEPROM-SPD-configuration */
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
- set_spd_default_value(2, 4); /* SDRAM Type */
- set_spd_default_value(7, 0); /* module width, high byte */
- set_spd_default_value(12, 1); /* Refresh or 0x81 */
-
- /* Only correct for HCU3 with 32 MB RAM*/
- /* Number of bytes used by module manufacturer */
- set_spd_default_value( 0, 128);
- set_spd_default_value( 1, 11 ); /* Total SPD memory size */
- set_spd_default_value( 2, 4 ); /* Memory type */
- set_spd_default_value( 3, 12 ); /* Number of row address bits */
- set_spd_default_value( 4, 9 ); /* Number of column address bits */
- set_spd_default_value( 5, 1 ); /* Number of module rows */
- set_spd_default_value( 6, 32 ); /* Module data width, LSB */
- set_spd_default_value( 7, 0 ); /* Module data width, MSB */
- set_spd_default_value( 8, 1 ); /* Module interface signal levels */
- /* SDRAM cycle time for highest CL (Tclk) */
- set_spd_default_value( 9, 112);
- /* SDRAM access time from clock for highest CL (Tac) */
- set_spd_default_value(10, 84 );
- set_spd_default_value(11, 2 ); /* Module configuration type */
- set_spd_default_value(12, 128); /* Refresh rate/type */
- set_spd_default_value(13, 16 ); /* Primary SDRAM width */
- set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */
- /* SDRAM device attributes, min clock delay for back to back */
- /*random column addresses (Tccd) */
- set_spd_default_value(15, 1 );
- /* SDRAM device attributes, burst lengths supported */
- set_spd_default_value(16, 143);
- /* SDRAM device attributes, number of banks on SDRAM device */
- set_spd_default_value(17, 4 );
- /* SDRAM device attributes, CAS latency */
- set_spd_default_value(18, 6 );
- /* SDRAM device attributes, CS latency */
- set_spd_default_value(19, 1 );
- /* SDRAM device attributes, WE latency */
- set_spd_default_value(20, 1 );
- set_spd_default_value(21, 0 ); /* SDRAM module attributes */
- /* SDRAM device attributes, general */
- set_spd_default_value(22, 14 );
- /* SDRAM cycle time for 2nd highest CL (Tclk) */
- set_spd_default_value(23, 117);
- /* SDRAM access time from clock for2nd highest CL (Tac) */
- set_spd_default_value(24, 84 );
- /* SDRAM cycle time for 3rd highest CL (Tclk) */
- set_spd_default_value(25, 0 );
- /* SDRAM access time from clock for3rd highest CL (Tac) */
- set_spd_default_value(26, 0 );
- set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */
- /* Minimum row active to row active delay (Trrd) */
- set_spd_default_value(28, 14 );
- set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */
- set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */
- set_spd_default_value(31, 8 ); /* Module bank density */
- /* Command and Address signal input setup time */
- set_spd_default_value(32, 21 );
- /* Command and Address signal input hold time */
- set_spd_default_value(33, 8 );
- set_spd_default_value(34, 21 ); /* Data signal input setup time */
- set_spd_default_value(35, 8 ); /* Data signal input hold time */
-#endif /* DO_UGLY_SDRAM_WORKAROUND */
- dram_size = spd_sdram(0);
-#endif