-#define LEC_LEN_ADDR 0x3A
-#define LEC_POWR_ADDR 0x3B
-#define LEC_DELP_ADDR 0x3C
-#define LEC_DELQ_ADDR 0x3D
-#define LEC_GAIN_XI_ADDR 0x3E
-#define LEC_GAIN_RI_ADDR 0x3F
-#define LEC_GAIN_XO_ADDR 0x40
-#define LEC_RES_1_ADDR 0x41
+#define LEC_LEN_ADDR 0x3A
+#define LEC_POWR_ADDR 0x3B
+#define LEC_DELP_ADDR 0x3C
+#define LEC_DELQ_ADDR 0x3D
+#define LEC_GAIN_XI_ADDR 0x3E
+#define LEC_GAIN_RI_ADDR 0x3F
+#define LEC_GAIN_XO_ADDR 0x40
+#define LEC_RES_1_ADDR 0x41
-#define UTD_CF_H_ADDR 0x4B
-#define UTD_CF_L_ADDR 0x4C
-#define UTD_BW_H_ADDR 0x4D
-#define UTD_BW_L_ADDR 0x4E
-#define UTD_NLEV_ADDR 0x4F
-#define UTD_SLEV_H_ADDR 0x50
-#define UTD_SLEV_L_ADDR 0x51
-#define UTD_DELT_ADDR 0x52
-#define UTD_RBRK_ADDR 0x53
-#define UTD_RTIME_ADDR 0x54
-#define UTD_EBRK_ADDR 0x55
-#define UTD_ETIME_ADDR 0x56
+#define UTD_CF_H_ADDR 0x4B
+#define UTD_CF_L_ADDR 0x4C
+#define UTD_BW_H_ADDR 0x4D
+#define UTD_BW_L_ADDR 0x4E
+#define UTD_NLEV_ADDR 0x4F
+#define UTD_SLEV_H_ADDR 0x50
+#define UTD_SLEV_L_ADDR 0x51
+#define UTD_DELT_ADDR 0x52
+#define UTD_RBRK_ADDR 0x53
+#define UTD_RTIME_ADDR 0x54
+#define UTD_EBRK_ADDR 0x55
+#define UTD_ETIME_ADDR 0x56
#define RO1_START_ADDR 0x70
#define RO2_START_ADDR 0x95
#define RO3_START_ADDR 0x96
#define TG1_FREQ_START_ADDR 0x38
#define TG1_GAIN_START_ADDR 0x39
#define RO1_START_ADDR 0x70
#define RO2_START_ADDR 0x95
#define RO3_START_ADDR 0x96
#define TG1_FREQ_START_ADDR 0x38
#define TG1_GAIN_START_ADDR 0x39
-#define BCR3_PCMX_EN (1 << 4)
-
-#define BCR5_DTMF_EN (1 << 0)
-#define BCR5_DTMF_SRC (1 << 1)
-#define BCR5_LEC_EN (1 << 2)
-#define BCR5_LEC_OUT (1 << 3)
-#define BCR5_CIS_EN (1 << 4)
-#define BCR5_CIS_AUTO (1 << 5)
-#define BCR5_UTDX_EN (1 << 6)
-#define BCR5_UTDR_EN (1 << 7)
-
-#define DSCR_TG1_EN (1 << 0)
-#define DSCR_TG2_EN (1 << 1)
-#define DSCR_PTG (1 << 2)
-#define DSCR_COR8 (1 << 3)
-#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4)
-
-#define CIS_LEC_MODE_CIS_V23 (1 << 0)
-#define CIS_LEC_MODE_CIS_FRM (1 << 1)
-#define CIS_LEC_MODE_NLP_EN (1 << 2)
-#define CIS_LEC_MODE_UTDR_SUM (1 << 4)
-#define CIS_LEC_MODE_UTDX_SUM (1 << 5)
+#define BCR3_PCMX_EN (1 << 4)
+
+#define BCR5_DTMF_EN (1 << 0)
+#define BCR5_DTMF_SRC (1 << 1)
+#define BCR5_LEC_EN (1 << 2)
+#define BCR5_LEC_OUT (1 << 3)
+#define BCR5_CIS_EN (1 << 4)
+#define BCR5_CIS_AUTO (1 << 5)
+#define BCR5_UTDX_EN (1 << 6)
+#define BCR5_UTDR_EN (1 << 7)
+
+#define DSCR_TG1_EN (1 << 0)
+#define DSCR_TG2_EN (1 << 1)
+#define DSCR_PTG (1 << 2)
+#define DSCR_COR8 (1 << 3)
+#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4)
+
+#define CIS_LEC_MODE_CIS_V23 (1 << 0)
+#define CIS_LEC_MODE_CIS_FRM (1 << 1)
+#define CIS_LEC_MODE_NLP_EN (1 << 2)
+#define CIS_LEC_MODE_UTDR_SUM (1 << 4)
+#define CIS_LEC_MODE_UTDX_SUM (1 << 5)
#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */
#define DIVIDER_RATIO_ACCURx100 (22 * 100)
#define V_AD_x10000 10834L /* VAD = 1.0834 */
#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */
#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */
#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */
#define DIVIDER_RATIO_ACCURx100 (22 * 100)
#define V_AD_x10000 10834L /* VAD = 1.0834 */
#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */
#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */
-#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/
-#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */
-#define K_INTDC_RECT_OFF 2 /* 2^2 */
-#define RNG_FREQ 25
-#define SAMPLING_FREQ (2000L)
-#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
-#define HOOK_THRESH_RING_START_ADDR 0x8B
-#define RING_PARAMS_START_ADDR 0x70
+#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/
+#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */
+#define K_INTDC_RECT_OFF 2 /* 2^2 */
+#define RNG_FREQ 25
+#define SAMPLING_FREQ (2000L)
+#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
+#define HOOK_THRESH_RING_START_ADDR 0x8B
+#define RING_PARAMS_START_ADDR 0x70
- memcpy(cmd + 2, block, len);
- codsp_send(duslic_id, cmd, 2 + len, 0, 0);
+ memcpy (cmd + 2, block, len);
+ codsp_send (duslic_id, cmd, 2 + len, 0, 0);
struct _coeffs ac_coeffs[11] = {
{ 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
struct _coeffs ac_coeffs[11] = {
{ 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
- { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */
- { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */
- { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */
- { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */
- { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */
- { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */
+ { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */
+ { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */
+ { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */
+ { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */
+ { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */
+ { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */
{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
{ 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
{ 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */
{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
{ 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
{ 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */
struct _coeffs dc_coeffs[9] = {
{ 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */
struct _coeffs dc_coeffs[9] = {
{ 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */
- { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */
- { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */
+ { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */
+ { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */
{ 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */
{ 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */
{ 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */
{ 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */
- { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */
- { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */
- { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */
- { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */
+ { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */
+ { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */
+ { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */
+ { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */
codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
break;
codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
break;
{
short LM_Result, Offset_Compensation; /* Signed 16 bit */
long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
{
short LM_Result, Offset_Compensation; /* Signed 16 bit */
long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
- b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
- codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
- (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
- udelay(80000);
+ b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+ codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+ (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
+ udelay(80000);
- b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
- codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
- b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+ b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+ codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+ b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
- b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
- codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
- b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+ b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
+ codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+ b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
- "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
- slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
+ "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
+ slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);