+#if defined(CONFIG_NETTA_6412)
+
+#define DRAM_REGS_BASE 0x1800000
+
+#define GBLCTL DRAM_REGS_BASE
+#define CECTL1 (DRAM_REGS_BASE + 0x4)
+#define CECTL0 (DRAM_REGS_BASE + 0x8)
+#define CECTL2 (DRAM_REGS_BASE + 0x10)
+#define CECTL3 (DRAM_REGS_BASE + 0x14)
+#define SDCTL (DRAM_REGS_BASE + 0x18)
+#define SDTIM (DRAM_REGS_BASE + 0x1C)
+#define SDEXT (DRAM_REGS_BASE + 0x20)
+#define SESEC1 (DRAM_REGS_BASE + 0x44)
+#define SESEC0 (DRAM_REGS_BASE + 0x48)
+#define SESEC2 (DRAM_REGS_BASE + 0x50)
+#define SESEC3 (DRAM_REGS_BASE + 0x54)
+
+#define MAR128 0x1848200
+#define MAR129 0x1848204
+
+void dsp_dram_initialize(void)
+{
+ c62_write_word(GBLCTL, 0x120E4);
+ c62_write_word(CECTL1, 0x18);
+ c62_write_word(CECTL0, 0xD0);
+ c62_write_word(CECTL2, 0x18);
+ c62_write_word(CECTL3, 0x18);
+ c62_write_word(SDCTL, 0x47115000);
+ c62_write_word(SDTIM, 1536);
+ c62_write_word(SDEXT, 0x534A9);
+#if 0
+ c62_write_word(SESEC1, 0);
+ c62_write_word(SESEC0, 0);
+ c62_write_word(SESEC2, 0);
+ c62_write_word(SESEC3, 0);
+#endif
+ c62_write_word(MAR128, 1);
+ c62_write_word(MAR129, 0);
+}
+
+#endif
+
+static inline void dsp_init_hpic(void)
+{
+ int i;
+ volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+ dsp_go_fast();
+#else
+ dsp_go_slow();
+#endif
+ i = 0;
+#if defined(CONFIG_NETTA_6412)
+ while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
+#else
+ while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
+#endif
+ dsp_delay();
+ i++;
+ }
+
+ if (i == 1000)
+ printf("HRDY stuck\n");
+
+ dsp_delay();
+
+ /* write control register */
+ p = (volatile u16 *)DSP_BASE;
+ p[0] = 0x0000;
+ dsp_delay();
+ p[1] = 0x0000;
+ dsp_delay();
+
+#if !defined(CONFIG_NETTA_6412)
+ dsp_go_fast();
+#endif
+}
+