- /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */
+ /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */
/* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */
/* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */
/* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */
/* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */
/* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */
/* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */
- volatile uchar *ramaddr0 = (uchar *) (CFG_SDRAM0_BASE);
- volatile uchar *ramaddr1 = (uchar *) (CFG_SDRAM1_BASE);
- ulong psdmr = CFG_PSDMR;
- volatile uchar *ramaddr2 = (uchar *) (CFG_SDRAM2_BASE);
- ulong lsdmr = CFG_LSDMR;
+ volatile uchar *ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE);
+ volatile uchar *ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE);
+ ulong psdmr = CONFIG_SYS_PSDMR;
+ volatile uchar *ramaddr2 = (uchar *) (CONFIG_SYS_SDRAM2_BASE);
+ ulong lsdmr = CONFIG_SYS_LSDMR;
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- ramaddr0 = (uchar *) (CFG_SDRAM0_BASE + 0x110);
- ramaddr1 = (uchar *) (CFG_SDRAM1_BASE + 0x110);
+ ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE + 0x110);
+ ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE + 0x110);
}
#ifdef CONFIG_MISC_INIT_R
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
}
#ifdef CONFIG_MISC_INIT_R
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{