- /* select video pll for ldb_di0_clk */
- reg = readl(&ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
- writel(reg, &ccm->cs2cdr);
-
- /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
- reg = readl(&ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &ccm->cscmr2);
+ /* gate ipu1_di0_clk */
+ reg = readl(&ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &ccm->CCGR3);