- /* Set DTR active */
- outb(inb (UART0_BASE + UART_MCR) | 0x01, UART0_BASE + UART_MCR);
- /* Start flow by setting RTS active */
- outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR);
- /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
- outb((1 << 6) | 1, UART0_BASE + UART_FCR);
+
+ /* Set DTR and RTS active, enable interrupts */
+ outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR);
+
+ /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
+ outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR);
+
+ serial_buffer_active = 1;