-#define MMU_Control_M 0x001 // Enable MMU
-#define MMU_Control_A 0x002 // Enable address alignment faults
-#define MMU_Control_C 0x004 // Enable cache
-#define MMU_Control_W 0x008 // Enable write-buffer
-#define MMU_Control_P 0x010 // Compatability: 32 bit code
-#define MMU_Control_D 0x020 // Compatability: 32 bit data
-#define MMU_Control_L 0x040 // Compatability:
-#define MMU_Control_B 0x080 // Enable Big-Endian
-#define MMU_Control_S 0x100 // Enable system protection
-#define MMU_Control_R 0x200 // Enable ROM protection
-#define MMU_Control_I 0x1000 // Enable Instruction cache
-#define MMU_Control_X 0x2000 // Set interrupt vectors at 0xFFFF0000
+#define MMU_Control_M 0x001 /* Enable MMU */
+#define MMU_Control_A 0x002 /* Enable address alignment faults */
+#define MMU_Control_C 0x004 /* Enable cache */
+#define MMU_Control_W 0x008 /* Enable write-buffer */
+#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
+#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
+#define MMU_Control_L 0x040 /* Compatability: */
+#define MMU_Control_B 0x080 /* Enable Big-Endian */
+#define MMU_Control_S 0x100 /* Enable system protection */
+#define MMU_Control_R 0x200 /* Enable ROM protection */
+#define MMU_Control_I 0x1000 /* Enable Instruction cache */
+#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */