- /*
- * Determine size of each TLB1 entry.
- */
- switch (memsize_in_meg) {
- case 16:
- case 32:
- tlb_size = BOOKE_PAGESZ_16M;
- break;
- case 64:
- case 128:
- tlb_size = BOOKE_PAGESZ_64M;
- break;
- case 256:
- case 512:
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- case 1024:
- case 2048:
- if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
- tlb_size = BOOKE_PAGESZ_1G;
- else
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- default:
- puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
- " and 2G are supported.\n");
-
- /*
- * The memory was not able to be mapped.
- * Default to a small size.
- */
- tlb_size = BOOKE_PAGESZ_64M;
- memsize_in_meg = 64;
- break;
- }
+ size = min(memsize, CONFIG_MAX_MEM_MAPPED);
+
+ /* Convert (4^max) kB to (2^max) bytes */
+ max_cam = max_cam * 2 + 10;
+
+ for (; size && ram_tlb_index < 16; ram_tlb_index++) {
+ u32 camsize = __ilog2_u64(size) & ~1U;
+ u32 align = __ilog2(ram_tlb_address) & ~1U;
+
+ if (align == -2) align = max_cam;
+ if (camsize > align)
+ camsize = align;
+
+ if (camsize > max_cam)
+ camsize = max_cam;
+
+ tlb_size = (camsize - 10) / 2;