-
- } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
- /*
- * busfreq 90~230 range, treated as DDR 200.
- */
- effective_data_rate = 200;
- if (spd.clk_cycle3 == 0xa0) /* 10 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0xa0)
- caslat--;
-
- } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
- /*
- * busfreq 230~280 range, treated as DDR 266.
- */
- effective_data_rate = 266;
- if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x75)
- caslat--;
-
- } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
- /*
- * busfreq 280~350 range, treated as DDR 333.
- */
- effective_data_rate = 333;
- if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x60)
- caslat--;
-
- } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
- /*
- * busfreq 350~460 range, treated as DDR 400.
- */
- effective_data_rate = 400;
- if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x50)
- caslat--;
-
- } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
- /*
- * busfreq 460~560 range, treated as DDR 533.
- */
- effective_data_rate = 533;
- if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x3D)
- caslat--;
-
- } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
- /*
- * busfreq 560~700 range, treated as DDR 667.
- */
- effective_data_rate = 667;
- if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x30)
- caslat--;
-
- } else if (700 <= busfreq) {
- /*
- * DDR rate out-of-range
- */
- printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
- busfreq, max_data_rate);