+#elif defined(CONFIG_STM32F1)
+#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
+#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
+#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
+#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
+#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
+#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
+#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
+
+static const unsigned long io_base[] = {
+ STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
+ STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
+ STM32_GPIOG_BASE
+};
+
+#define STM32_GPIO_CR_MODE_MASK 0x3
+#define STM32_GPIO_CR_MODE_SHIFT(p) (p * 4)
+#define STM32_GPIO_CR_CNF_MASK 0x3
+#define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2)
+
+struct stm32_gpio_regs {
+ u32 crl; /* GPIO port configuration low */
+ u32 crh; /* GPIO port configuration high */
+ u32 idr; /* GPIO port input data */
+ u32 odr; /* GPIO port output data */
+ u32 bsrr; /* GPIO port bit set/reset */
+ u32 brr; /* GPIO port bit reset */
+ u32 lckr; /* GPIO port configuration lock */
+};
+
+#define CHECK_DSC(x) (!x || x->port > 6 || x->pin > 15)
+#define CHECK_CTL(x) (!x || x->mode > 3 || x->icnf > 3 || x->ocnf > 3 || \
+ x->pupd > 1)
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
+ const struct stm32_gpio_ctl *ctl)
+{
+ struct stm32_gpio_regs *gpio_regs;
+ u32 *cr;
+ int p, crp;
+ int rv;
+
+ if (CHECK_DSC(dsc)) {
+ rv = -EINVAL;
+ goto out;
+ }
+ if (CHECK_CTL(ctl)) {
+ rv = -EINVAL;
+ goto out;
+ }
+
+ p = dsc->pin;
+
+ gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
+
+ /* Enable clock for GPIO port */
+ setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port);
+
+ if (p < 8) {
+ cr = &gpio_regs->crl;
+ crp = p;
+ } else {
+ cr = &gpio_regs->crh;
+ crp = p - 8;
+ }
+
+ clrbits_le32(cr, 0x3 << STM32_GPIO_CR_MODE_SHIFT(crp));
+ setbits_le32(cr, ctl->mode << STM32_GPIO_CR_MODE_SHIFT(crp));
+
+ clrbits_le32(cr, 0x3 << STM32_GPIO_CR_CNF_SHIFT(crp));
+ /* Inputs set the optional pull up / pull down */
+ if (ctl->mode == STM32_GPIO_MODE_IN) {
+ setbits_le32(cr, ctl->icnf << STM32_GPIO_CR_CNF_SHIFT(crp));
+ clrbits_le32(&gpio_regs->odr, 0x1 << p);
+ setbits_le32(&gpio_regs->odr, ctl->pupd << p);
+ } else {
+ setbits_le32(cr, ctl->ocnf << STM32_GPIO_CR_CNF_SHIFT(crp));
+ }
+
+ rv = 0;
+out:
+ return rv;
+}
+#else
+#error STM32 family not supported
+#endif