- clrbits_le32(&gpio_regs->moder, (0x3 << i));
- setbits_le32(&gpio_regs->moder, ctl->mode << i);
+ clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
+ clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
+ clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
+ clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
+
+ rv = 0;
+out:
+ return rv;
+}
+#elif defined(CONFIG_STM32F1)
+#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
+#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
+#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
+#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
+#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
+#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
+#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
+
+static const unsigned long io_base[] = {
+ STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
+ STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
+ STM32_GPIOG_BASE
+};