sunxi: Fix USB_GADGET implication

[u-boot] / drivers / misc / Kconfig

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 3b7f76ab78753c9ca6f2252b6130f536ffe3b961..f1c15cb9fa4060eb62a1606930eb5f6794e63509 100644 (file)
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -1,3 +1,46 @@
+#
+# Multifunction miscellaneous devices
+#
+
+menu "Multifunction device drivers"
+
+config MISC
+       bool "Enable Driver Model for Misc drivers"
+       depends on DM
+       help
+         Enable driver model for miscellaneous devices. This class is
+         used only for those do not fit other more general classes. A
+         set of generic read, write and ioctl methods may be used to
+         access the device.
+
+config ALTERA_SYSID
+       bool "Altera Sysid support"
+       depends on MISC
+       help
+         Select this to enable a sysid for Altera devices. Please find
+         details on the "Embedded Peripherals IP User Guide" of Altera.
+
+config ATSHA204A
+       bool "Support for Atmel ATSHA204A module"
+       depends on MISC
+       help
+          Enable support for I2C connected Atmel's ATSHA204A
+          CryptoAuthentication module found for example on the Turris Omnia
+          board.
+
+config ROCKCHIP_EFUSE
+        bool "Rockchip e-fuse support"
+       depends on MISC
+       help
+         Enable (read-only) access for the e-fuse block found in Rockchip
+         SoCs: accesses can either be made using byte addressing and a length
+         or through child-nodes that are generated based on the e-fuse map
+         retrieved from the DTS.
+
+         This driver currently supports the RK3399 only, but can easily be
+         extended (by porting the read function from the Linux kernel sources)
+         to support other recent Rockchip devices.
+

 config CMD_CROS_EC
        bool "Enable crosec command"
        depends on CROS_EC
 config CMD_CROS_EC
        bool "Enable crosec command"
        depends on CROS_EC


@@ -53,7 +96,15 @@ config CROS_EC_SPI
          provides a faster and more robust interface than I2C but the bugs
          are less interesting.
 
          provides a faster and more robust interface than I2C but the bugs
          are less interesting.
 

-config CONFIG_FSL_SEC_MON
+config DS4510
+       bool "Enable support for DS4510 CPU supervisor"
+       help
+         Enable support for the Maxim DS4510 CPU supervisor. It has an
+         integrated 64-byte EEPROM, four programmable non-volatile I/O pins
+         and a configurable timer for the supervisor function. The device is
+         connected over I2C.
+
+config FSL_SEC_MON

        bool "Enable FSL SEC_MON Driver"
        help
          Freescale Security Monitor block is responsible for monitoring
        bool "Enable FSL SEC_MON Driver"
        help
          Freescale Security Monitor block is responsible for monitoring


@@ -61,6 +112,39 @@ config CONFIG_FSL_SEC_MON
          Security Monitor can be transitioned on any security failures,
          like software violations or hardware security violations.
 
          Security Monitor can be transitioned on any security failures,
          like software violations or hardware security violations.
 

+config MXC_OCOTP
+       bool "Enable MXC OCOTP Driver"
+       help
+         If you say Y here, you will get support for the One Time
+         Programmable memory pages that are stored on the some
+         Freescale i.MX processors.
+
+config NUVOTON_NCT6102D
+       bool "Enable Nuvoton NCT6102D Super I/O driver"
+       help
+         If you say Y here, you will get support for the Nuvoton
+         NCT6102D Super I/O driver. This can be used to enable or
+         disable the legacy UART, the watchdog or other devices
+         in the Nuvoton Super IO chips on X86 platforms.
+
+config PWRSEQ
+       bool "Enable power-sequencing drivers"
+       depends on DM
+       help
+         Power-sequencing drivers provide support for controlling power for
+         devices. They are typically referenced by a phandle from another
+         device. When the device is started up, its power sequence can be
+         initiated.
+
+config SPL_PWRSEQ
+       bool "Enable power-sequencing drivers for SPL"
+       depends on PWRSEQ
+       help
+         Power-sequencing drivers provide support for controlling power for
+         devices. They are typically referenced by a phandle from another
+         device. When the device is started up, its power sequence can be
+         initiated.
+

 config PCA9551_LED
        bool "Enable PCA9551 LED driver"
        help
 config PCA9551_LED
        bool "Enable PCA9551 LED driver"
        help


@@ -74,11 +158,104 @@ config PCA9551_I2C_ADDR
        help
          The I2C address of the PCA9551 LED controller.
 
        help
          The I2C address of the PCA9551 LED controller.
 

-config RESET
-       bool "Enable support for reset drivers"
-       depends on DM
+config STM32_RCC
+       bool "Enable RCC driver for the STM32 SoC's family"
+       depends on STM32 && MISC
+       help
+         Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
+         block) is responsible of the management of the clock and reset
+         generation.
+         This driver is similar to an MFD driver in the Linux kernel.
+
+config TEGRA_CAR
+       bool "Enable support for the Tegra CAR driver"
+       depends on TEGRA_NO_BPMP

        help
        help

-         Enable reset drivers which can be used to reset the CPU or board.
-         Each driver can provide a reset method which will be called to
-         effect a reset. The uclass will try all available drivers when
-         reset_walk() is called.
+         The Tegra CAR (Clock and Reset Controller) is a HW module that
+         controls almost all clocks and resets in a Tegra SoC.
+
+config TEGRA186_BPMP
+       bool "Enable support for the Tegra186 BPMP driver"
+       depends on TEGRA186
+       help
+         The Tegra BPMP (Boot and Power Management Processor) is a separate
+         auxiliary CPU embedded into Tegra to perform power management work,
+         and controls related features such as clocks, resets, power domains,
+         PMIC I2C bus, etc. This driver provides the core low-level
+         communication path by which feature-specific drivers (such as clock)
+         can make requests to the BPMP. This driver is similar to an MFD
+         driver in the Linux kernel.
+
+config WINBOND_W83627
+       bool "Enable Winbond Super I/O driver"
+       help
+         If you say Y here, you will get support for the Winbond
+         W83627 Super I/O driver. This can be used to enable the
+         legacy UART or other devices in the Winbond Super IO chips
+         on X86 platforms.
+
+config QFW
+       bool
+       help
+         Hidden option to enable QEMU fw_cfg interface. This will be selected by
+         either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+
+config I2C_EEPROM
+       bool "Enable driver for generic I2C-attached EEPROMs"
+       depends on MISC
+       help
+         Enable a generic driver for EEPROMs attached via I2C.
+
+
+config SPL_I2C_EEPROM
+       bool "Enable driver for generic I2C-attached EEPROMs for SPL"
+       depends on MISC && SPL && SPL_DM
+       help
+         This option is an SPL-variant of the I2C_EEPROM option.
+         See the help of I2C_EEPROM for details.
+
+if I2C_EEPROM
+
+config SYS_I2C_EEPROM_ADDR
+       hex "Chip address of the EEPROM device"
+       default 0
+
+config SYS_I2C_EEPROM_BUS
+       int "I2C bus of the EEPROM device."
+       default 0
+
+config SYS_EEPROM_SIZE
+       int "Size in bytes of the EEPROM device"
+       default 256
+
+config SYS_EEPROM_PAGE_WRITE_BITS
+       int "Number of bits used to address bytes in a single page"
+       default 0
+       help
+         The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
+         A 64 byte page, for example would require six bits.
+
+config SYS_EEPROM_PAGE_WRITE_DELAY_MS
+       int "Number of milliseconds to delay between page writes"
+       default 0
+
+config SYS_I2C_EEPROM_ADDR_LEN
+       int "Length in bytes of the EEPROM memory array address"
+       default 1
+       help
+         Note: This is NOT the chip address length!
+
+config SYS_I2C_EEPROM_ADDR_OVERFLOW
+       hex "EEPROM Address Overflow"
+       default 0
+       help
+         EEPROM chips that implement "address overflow" are ones
+         like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+         address and the extra bits end up in the "chip address" bit
+         slots. This makes a 24WC08 (1Kbyte) chip look like four 256
+         byte chips.
+
+endif
+
+
+endmenu