+static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
+{
+ int ret = 0;
+ u32 timeout = 240000;
+ u32 mask, size, i, len = 0;
+ u32 *buf = NULL;
+ ulong start = get_timer(0);
+ u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
+ RX_WMARK_SHIFT) + 1) * 2;
+
+ size = data->blocksize * data->blocks / 4;
+ if (data->flags == MMC_DATA_READ)
+ buf = (unsigned int *)data->dest;
+ else
+ buf = (unsigned int *)data->src;
+
+ for (;;) {
+ mask = dwmci_readl(host, DWMCI_RINTSTS);
+ /* Error during data transfer. */
+ if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
+ debug("%s: DATA ERROR!\n", __func__);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (host->fifo_mode && size) {
+ len = 0;
+ if (data->flags == MMC_DATA_READ &&
+ (mask & DWMCI_INTMSK_RXDR)) {
+ while (size) {
+ len = dwmci_readl(host, DWMCI_STATUS);
+ len = (len >> DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK;
+ len = min(size, len);
+ for (i = 0; i < len; i++)
+ *buf++ =
+ dwmci_readl(host, DWMCI_DATA);
+ size = size > len ? (size - len) : 0;
+ }
+ dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_RXDR);
+ } else if (data->flags == MMC_DATA_WRITE &&
+ (mask & DWMCI_INTMSK_TXDR)) {
+ while (size) {
+ len = dwmci_readl(host, DWMCI_STATUS);
+ len = fifo_depth - ((len >>
+ DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK);
+ len = min(size, len);
+ for (i = 0; i < len; i++)
+ dwmci_writel(host, DWMCI_DATA,
+ *buf++);
+ size = size > len ? (size - len) : 0;
+ }
+ dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_TXDR);
+ }
+ }
+
+ /* Data arrived correctly. */
+ if (mask & DWMCI_INTMSK_DTO) {
+ ret = 0;
+ break;
+ }
+
+ /* Check for timeout. */
+ if (get_timer(start) > timeout) {
+ debug("%s: Timeout waiting for data!\n",
+ __func__);
+ ret = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ dwmci_writel(host, DWMCI_RINTSTS, mask);
+
+ return ret;
+}
+