+/* registers */
+#define NFC_CTL 0x00000000
+#define NFC_ST 0x00000004
+#define NFC_INT 0x00000008
+#define NFC_TIMING_CTL 0x0000000C
+#define NFC_TIMING_CFG 0x00000010
+#define NFC_ADDR_LOW 0x00000014
+#define NFC_ADDR_HIGH 0x00000018
+#define NFC_SECTOR_NUM 0x0000001C
+#define NFC_CNT 0x00000020
+#define NFC_CMD 0x00000024
+#define NFC_RCMD_SET 0x00000028
+#define NFC_WCMD_SET 0x0000002C
+#define NFC_IO_DATA 0x00000030
+#define NFC_ECC_CTL 0x00000034
+#define NFC_ECC_ST 0x00000038
+#define NFC_DEBUG 0x0000003C
+#define NFC_ECC_CNT0 0x00000040
+#define NFC_ECC_CNT1 0x00000044
+#define NFC_ECC_CNT2 0x00000048
+#define NFC_ECC_CNT3 0x0000004C
+#define NFC_USER_DATA_BASE 0x00000050
+#define NFC_EFNAND_STATUS 0x00000090
+#define NFC_SPARE_AREA 0x000000A0
+#define NFC_PATTERN_ID 0x000000A4
+#define NFC_RAM0_BASE 0x00000400
+#define NFC_RAM1_BASE 0x00000800
+
+#define NFC_CTL_EN (1 << 0)
+#define NFC_CTL_RESET (1 << 1)
+#define NFC_CTL_RAM_METHOD (1 << 14)
+#define NFC_CTL_PAGE_SIZE_MASK (0xf << 8)
+#define NFC_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
+
+
+#define NFC_ECC_EN (1 << 0)
+#define NFC_ECC_PIPELINE (1 << 3)
+#define NFC_ECC_EXCEPTION (1 << 4)
+#define NFC_ECC_BLOCK_SIZE (1 << 5)
+#define NFC_ECC_RANDOM_EN (1 << 9)
+#define NFC_ECC_RANDOM_DIRECTION (1 << 10)
+
+
+#define NFC_ADDR_NUM_OFFSET 16
+#define NFC_SEND_ADR (1 << 19)
+#define NFC_ACCESS_DIR (1 << 20)
+#define NFC_DATA_TRANS (1 << 21)
+#define NFC_SEND_CMD1 (1 << 22)
+#define NFC_WAIT_FLAG (1 << 23)
+#define NFC_SEND_CMD2 (1 << 24)
+#define NFC_SEQ (1 << 25)
+#define NFC_DATA_SWAP_METHOD (1 << 26)
+#define NFC_ROW_AUTO_INC (1 << 27)
+#define NFC_SEND_CMD3 (1 << 28)
+#define NFC_SEND_CMD4 (1 << 29)
+
+#define NFC_ST_CMD_INT_FLAG (1 << 1)
+#define NFC_ST_DMA_INT_FLAG (1 << 2)
+
+#define NFC_READ_CMD_OFFSET 0
+#define NFC_RANDOM_READ_CMD0_OFFSET 8
+#define NFC_RANDOM_READ_CMD1_OFFSET 16
+
+#define NFC_CMD_RNDOUTSTART 0xE0
+#define NFC_CMD_RNDOUT 0x05
+#define NFC_CMD_READSTART 0x30
+
+
+#define NFC_PAGE_CMD (2 << 30)
+
+#define SUNXI_DMA_CFG_REG0 0x300
+#define SUNXI_DMA_SRC_START_ADDR_REG0 0x304
+#define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
+#define SUNXI_DMA_DDMA_BC_REG0 0x30C
+#define SUNXI_DMA_DDMA_PARA_REG0 0x318
+
+#define SUNXI_DMA_DDMA_CFG_REG_LOADING (1 << 31)
+#define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
+#define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
+#define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
+#define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
+#define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
+
+#define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
+#define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
+
+/* minimal "boot0" style NAND support for Allwinner A20 */
+
+/* random seed used by linux */
+const uint16_t random_seed[128] = {