#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
hw_p->tx = (mal_desc_t *)(bd_uncached);
hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
hw_p->tx = (mal_desc_t *)(bd_uncached);
hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
- debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
+ debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
{
struct enet_frame *ef_ptr;
ulong time_start, time_now;
{
struct enet_frame *ef_ptr;
ulong time_start, time_now;
/* check for EOB on valid channels */
if (uic_mal & UIC_MAL_RXEOB) {
mal_eob = mfdcr(MAL0_RXEOBISR);
/* check for EOB on valid channels */
if (uic_mal & UIC_MAL_RXEOB) {
mal_eob = mfdcr(MAL0_RXEOBISR);
*-----------------------------------------------------------------------------*/
static void enet_rcv (struct eth_device *dev, unsigned long malisr)
{
*-----------------------------------------------------------------------------*/
static void enet_rcv (struct eth_device *dev, unsigned long malisr)
{