- *pDMA1_CONFIG = 0x0000;
- *pDMA2_CONFIG = 0x0000;
-
-}
-
-void bfin_EMAC_setup_addr(bd_t *bd)
-{
- *pEMAC_ADDRLO =
- bd->bi_enetaddr[0] |
- bd->bi_enetaddr[1] << 8 |
- bd->bi_enetaddr[2] << 16 |
- bd->bi_enetaddr[3] << 24;
- *pEMAC_ADDRHI =
- bd->bi_enetaddr[4] |
- bd->bi_enetaddr[5] << 8;
-}
-
-static void PollMdcDone(void)
-{
- /* poll the STABUSY bit */
- while (*pEMAC_STAADD & STABUSY) ;
-}
-
-static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
-{
- PollMdcDone();
-
- *pEMAC_STADAT = Data;
-
- *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
- STAOP | STAIE | STABUSY;
-}
-
-/*********************************************************************************
- * Read an off-chip register in a PHY through the MDC/MDIO port *
- *********************************************************************************/
-static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
-{
- u16 Data;
-
- PollMdcDone();
-
- *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
- STAIE | STABUSY;
-
- PollMdcDone();
-
- Data = (u16) * pEMAC_STADAT;
-
- PHYregs[RegAddr] = Data; /* save shadow copy */
-
- return Data;
-}
-
-#if 0 /* dead code ? */
-static void SoftResetPHY(void)
-{
- u16 phydat;
- /* set the reset bit */
- WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
- /* and clear it again */
- WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
- do {
- /* poll until reset is complete */
- phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
- } while ((phydat & PHY_RESET) != 0);
-}
-#endif
-
-static int SetupSystemRegs(int *opmode)
-{
- u16 sysctl, phydat;
- int count = 0;
- /* Enable PHY output */
- *pVR_CTL |= CLKBUFOE;
- /* Set all the pins to peripheral mode */
-
-#ifdef CONFIG_BFIN_MAC_RMII
- /* grab RMII pins */
-# if defined(__ADSPBF51x__)
- *pPORTF_MUX = (*pPORTF_MUX & \
- ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
- PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
- *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
- *pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
- *pPORTG_FER |= PG14 | PG15;
- *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
- PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
- *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
-# else
- *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
-# endif
-#else
- /* grab MII & RMII pins */
-# if defined(__ADSPBF51x__)
- *pPORTF_MUX = (*pPORTF_MUX & \
- ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
- PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
- *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
- *pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
- *pPORTG_FER |= PG14 | PG15;
- *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
- *pPORTH_FER = -1; /* all pins */
-# else
- *pPORTH_FER = -1; /* all pins */
-# endif
-#endif
-
- /* MDC = 2.5 MHz */
- sysctl = SET_MDCDIV(24);
- /* Odd word alignment for Receive Frame DMA word */
- /* Configure checksum support and rcve frame word alignment */
- sysctl |= RXDWA | RXCKS;
- *pEMAC_SYSCTL = sysctl;
- /* auto negotiation on */
- /* full duplex */
- /* 100 Mbps */
- phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
- WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
- do {
- udelay(1000);
- phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
- if (count > 3000) {
- printf
- ("Link is down, please check your network connection\n");
- return -1;
- }
- count++;
- } while (!(phydat & 0x0004));
-
- phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
-
- if ((phydat & 0x0100) || (phydat & 0x0040))
- *opmode = FDMODE;
- else
- *opmode = 0;
-
- *pEMAC_MMC_CTL = RSTC | CROLL;
-
- /* Initialize the TX DMA channel registers */
- *pDMA2_X_COUNT = 0;
- *pDMA2_X_MODIFY = 4;
- *pDMA2_Y_COUNT = 0;
- *pDMA2_Y_MODIFY = 0;
-
- /* Initialize the RX DMA channel registers */
- *pDMA1_X_COUNT = 0;
- *pDMA1_X_MODIFY = 4;
- *pDMA1_Y_COUNT = 0;
- *pDMA1_Y_MODIFY = 0;
- return 0;