- /* Change the rclk and clk only not using EMIO interface */
- if (!priv->emio)
- zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
- ZYNQ_GEM_BASEADDR0, clk_rate);
+ ret = clk_set_rate(&priv->clk, clk_rate);
+ if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
+ dev_err(dev, "failed to set tx clock rate\n");
+ return ret;
+ }
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable tx clock\n");
+ return ret;
+ }