+ debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
+ reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
+ MXC_CSPICTRL_SELCHAN(cs);
+ reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
+ MXC_CSPICTRL_PREDIV(pre_div);
+ reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
+ MXC_CSPICTRL_POSTDIV(post_div);
+
+ /* always set to master mode */
+ reg_ctrl |= 1 << (cs + 4);
+
+ /* We need to disable SPI before changing registers */
+ reg_ctrl &= ~MXC_CSPICTRL_EN;
+
+ if (mode & SPI_CS_HIGH)
+ ss_pol = 1;
+
+ if (mode & SPI_CPOL)
+ sclkpol = 1;
+
+ if (mode & SPI_CPHA)
+ sclkpha = 1;
+
+ reg_config = reg_read(®s->cfg);
+
+ /*
+ * Configuration register setup
+ * The MX51 supports different setup for each SS
+ */
+ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
+ (ss_pol << (cs + MXC_CSPICON_SSPOL));
+ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
+ (sclkpol << (cs + MXC_CSPICON_POL));
+ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
+ (sclkpha << (cs + MXC_CSPICON_PHA));
+
+ debug("reg_ctrl = 0x%x\n", reg_ctrl);
+ reg_write(®s->ctrl, reg_ctrl);
+ debug("reg_config = 0x%x\n", reg_config);
+ reg_write(®s->cfg, reg_config);
+
+ /* save config register and control register */
+ mxcs->ctrl_reg = reg_ctrl;
+ mxcs->cfg_reg = reg_config;
+
+ /* clear interrupt reg */
+ reg_write(®s->intr, 0);
+ reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
+
+ return 0;
+}
+#endif
+
+int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
+ const u8 *dout, u8 *din, unsigned long flags)
+{
+ struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ int nbytes = (bitlen + 7) / 8;
+ u32 data, cnt, i;
+ struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
+
+ debug("%s: bitlen %d dout 0x%x din 0x%x\n",
+ __func__, bitlen, (u32)dout, (u32)din);
+
+ mxcs->ctrl_reg = (mxcs->ctrl_reg &
+ ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
+ MXC_CSPICTRL_BITCOUNT(bitlen - 1);
+
+ reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
+#ifdef MXC_ECSPI
+ reg_write(®s->cfg, mxcs->cfg_reg);
+#endif
+
+ /* Clear interrupt register */
+ reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
+
+ /*
+ * The SPI controller works only with words,
+ * check if less than a word is sent.
+ * Access to the FIFO is only 32 bit
+ */
+ if (bitlen % 32) {
+ data = 0;
+ cnt = (bitlen % 32) / 8;
+ if (dout) {
+ for (i = 0; i < cnt; i++) {
+ data = (data << 8) | (*dout++ & 0xFF);
+ }
+ }
+ debug("Sending SPI 0x%x\n", data);
+
+ reg_write(®s->txdata, data);
+ nbytes -= cnt;
+ }