+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct omap3_spi_priv *priv;
+ struct mcspi *regs;
+
+ /*
+ * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
+ * with different number of chip selects (CS, channels):
+ * McSPI1 has 4 CS (bus 0, cs 0 - 3)
+ * McSPI2 has 2 CS (bus 1, cs 0 - 1)
+ * McSPI3 has 2 CS (bus 2, cs 0 - 1)
+ * McSPI4 has 1 CS (bus 3, cs 0)
+ */
+
+ switch (bus) {
+ case 0:
+ regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
+ break;
+#ifdef OMAP3_MCSPI2_BASE
+ case 1:
+ regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
+ break;
+#endif
+#ifdef OMAP3_MCSPI3_BASE
+ case 2:
+ regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
+ break;
+#endif
+#ifdef OMAP3_MCSPI4_BASE
+ case 3:
+ regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
+ break;
+#endif
+ default:
+ printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus);
+ return NULL;
+ }
+
+ if (((bus == 0) && (cs > 3)) ||
+ ((bus == 1) && (cs > 1)) ||
+ ((bus == 2) && (cs > 1)) ||
+ ((bus == 3) && (cs > 0))) {
+ printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus);
+ return NULL;
+ }
+
+ if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
+ printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n",
+ max_hz);
+ return NULL;
+ }
+
+ if (mode > SPI_MODE_3) {
+ printf("SPI error: unsupported SPI mode %i\n", mode);
+ return NULL;
+ }
+
+ priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
+ if (!priv) {
+ printf("SPI error: malloc of SPI structure failed\n");
+ return NULL;
+ }
+
+ priv->regs = regs;
+ priv->cs = cs;
+ priv->freq = max_hz;
+ priv->mode = mode;
+ priv->wordlen = priv->slave.wordlen;
+#if 0
+ /* Please migrate to DM_SPI support for this feature. */
+ priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+#endif
+
+ return &priv->slave;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct omap3_spi_priv *priv = to_omap3_spi(slave);
+
+ return _spi_xfer(priv, bitlen, dout, din, flags);
+}
+
+#else
+
+static int omap3_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct omap3_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ priv->cs = slave_plat->cs;
+ priv->freq = slave_plat->max_hz;
+
+ _omap3_spi_claim_bus(priv);
+
+ return 0;
+}
+
+static int omap3_spi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct omap3_spi_priv *priv = dev_get_priv(bus);
+
+ /* Reset the SPI hardware */
+ spi_reset(priv->regs);
+
+ return 0;
+}
+
+static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
+{
+ struct udevice *bus = dev->parent;
+ struct omap3_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ priv->cs = slave_plat->cs;
+ priv->wordlen = wordlen;
+ _omap3_spi_set_wordlen(priv);
+
+ return 0;
+}
+
+static int omap3_spi_probe(struct udevice *dev)
+{
+ struct omap3_spi_priv *priv = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+
+ struct omap2_mcspi_platform_config* data =
+ (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
+
+ priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
+ if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
+ priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+ else
+ priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
+ priv->wordlen = SPI_DEFAULT_WORDLEN;
+ return 0;
+}
+
+static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct omap3_spi_priv *priv = dev_get_priv(bus);
+
+ return _spi_xfer(priv, bitlen, dout, din, flags);
+}
+
+static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
+{
+
+ struct omap3_spi_priv *priv = dev_get_priv(dev);
+
+ priv->freq = speed;
+ _omap3_spi_set_speed(priv);
+
+ return 0;
+}
+
+static int omap3_spi_set_mode(struct udevice *dev, uint mode)
+{
+ struct omap3_spi_priv *priv = dev_get_priv(dev);
+
+ priv->mode = mode;
+
+ _omap3_spi_set_mode(priv);
+
+ return 0;
+}
+
+static const struct dm_spi_ops omap3_spi_ops = {
+ .claim_bus = omap3_spi_claim_bus,
+ .release_bus = omap3_spi_release_bus,
+ .set_wordlen = omap3_spi_set_wordlen,
+ .xfer = omap3_spi_xfer,
+ .set_speed = omap3_spi_set_speed,
+ .set_mode = omap3_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static struct omap2_mcspi_platform_config omap2_pdata = {
+ .regs_offset = 0,
+};
+
+static struct omap2_mcspi_platform_config omap4_pdata = {
+ .regs_offset = OMAP4_MCSPI_REG_OFFSET,
+};
+
+static const struct udevice_id omap3_spi_ids[] = {
+ { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
+ { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
+ { }
+};
+
+U_BOOT_DRIVER(omap3_spi) = {
+ .name = "omap3_spi",
+ .id = UCLASS_SPI,
+ .of_match = omap3_spi_ids,
+ .probe = omap3_spi_probe,
+ .ops = &omap3_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
+};
+#endif