- out_be32((void *)(addr + FSL_SOC_USB_PRICTRL), 0x0000000c);
- out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x00000040);
- out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x00000001);
+ if (!strncmp(phy_type, "utmi", 4)) {
+#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_UTMI);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ UTMI_PHY_EN);
+ udelay(1000); /* delay required for PHY Clk to appear */
+#endif
+ out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ USB_EN);
+ } else {
+ clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+ PHY_CLK_SEL_ULPI);
+ clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+ CONTROL_REGISTER_W1C_MASK, USB_EN);
+ udelay(1000); /* delay required for PHY Clk to appear */
+ if (!usb_phy_clk_valid(ehci))
+ return -EINVAL;
+ out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
+ }