- DISP_WR_REG (0x0004, (dev->winSizeX +
- res_mode->left_margin +
- res_mode->right_margin +
- res_mode->hsync_len - 1) << 16);
- DISP_WR_REG (0x0008, (dev->winSizeX - 1) << 16 | (dev->winSizeX - 1));
- DISP_WR_REG (0x000c, (res_mode->vsync_len - 1) << 24 |
- (res_mode->hsync_len - 1) << 16 |
- (dev->winSizeX + res_mode->right_margin - 1));
- DISP_WR_REG (0x0010, (dev->winSizeY + res_mode->lower_margin +
- res_mode->upper_margin +
- res_mode->vsync_len - 1) << 16);
- DISP_WR_REG (0x0014, (dev->winSizeY-1) << 16 |
- (dev->winSizeY + res_mode->lower_margin - 1));
- DISP_WR_REG (0x0018, 0x00000000);
- DISP_WR_REG (0x001c, dev->winSizeY << 16 | dev->winSizeX);
+ DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
+ res_mode->left_margin +
+ res_mode->right_margin +
+ res_mode->hsync_len - 1) << 16);
+ DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
+ (dev->winSizeX - 1));
+ DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
+ (res_mode->hsync_len - 1) << 16 |
+ (dev->winSizeX +
+ res_mode->right_margin - 1));
+ DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
+ res_mode->upper_margin +
+ res_mode->vsync_len - 1) << 16);
+ DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
+ (dev->winSizeY +
+ res_mode->lower_margin - 1));
+ DISP_WR_REG (GC_WY_WX, 0x0);
+ DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);