-#define DDAR0 /* DMA Device Address Reg. */ \
- /* channel 0 */ \
- (*((volatile Word *) io_p2v (_DDAR0)))
-#define SetDCSR0 /* Set DMA Control & Status Reg. */ \
- /* channel 0 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR0)))
-#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
- /* channel 0 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR0)))
-#define RdDCSR0 /* Read DMA Control & Status Reg. */ \
- /* channel 0 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR0)))
-#define DBSA0 /* DMA Buffer Start address reg. A */ \
- /* channel 0 */ \
- (*((volatile Address *) io_p2v (_DBSA0)))
-#define DBTA0 /* DMA Buffer Transfer count */ \
- /* reg. A channel 0 */ \
- (*((volatile Word *) io_p2v (_DBTA0)))
-#define DBSB0 /* DMA Buffer Start address reg. B */ \
- /* channel 0 */ \
- (*((volatile Address *) io_p2v (_DBSB0)))
-#define DBTB0 /* DMA Buffer Transfer count */ \
- /* reg. B channel 0 */ \
- (*((volatile Word *) io_p2v (_DBTB0)))
-
-#define DDAR1 /* DMA Device Address Reg. */ \
- /* channel 1 */ \
- (*((volatile Word *) io_p2v (_DDAR1)))
-#define SetDCSR1 /* Set DMA Control & Status Reg. */ \
- /* channel 1 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR1)))
-#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
- /* channel 1 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR1)))
-#define RdDCSR1 /* Read DMA Control & Status Reg. */ \
- /* channel 1 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR1)))
-#define DBSA1 /* DMA Buffer Start address reg. A */ \
- /* channel 1 */ \
- (*((volatile Address *) io_p2v (_DBSA1)))
-#define DBTA1 /* DMA Buffer Transfer count */ \
- /* reg. A channel 1 */ \
- (*((volatile Word *) io_p2v (_DBTA1)))
-#define DBSB1 /* DMA Buffer Start address reg. B */ \
- /* channel 1 */ \
- (*((volatile Address *) io_p2v (_DBSB1)))
-#define DBTB1 /* DMA Buffer Transfer count */ \
- /* reg. B channel 1 */ \
- (*((volatile Word *) io_p2v (_DBTB1)))
-
-#define DDAR2 /* DMA Device Address Reg. */ \
- /* channel 2 */ \
- (*((volatile Word *) io_p2v (_DDAR2)))
-#define SetDCSR2 /* Set DMA Control & Status Reg. */ \
- /* channel 2 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR2)))
-#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
- /* channel 2 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR2)))
-#define RdDCSR2 /* Read DMA Control & Status Reg. */ \
- /* channel 2 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR2)))
-#define DBSA2 /* DMA Buffer Start address reg. A */ \
- /* channel 2 */ \
- (*((volatile Address *) io_p2v (_DBSA2)))
-#define DBTA2 /* DMA Buffer Transfer count */ \
- /* reg. A channel 2 */ \
- (*((volatile Word *) io_p2v (_DBTA2)))
-#define DBSB2 /* DMA Buffer Start address reg. B */ \
- /* channel 2 */ \
- (*((volatile Address *) io_p2v (_DBSB2)))
-#define DBTB2 /* DMA Buffer Transfer count */ \
- /* reg. B channel 2 */ \
- (*((volatile Word *) io_p2v (_DBTB2)))
-
-#define DDAR3 /* DMA Device Address Reg. */ \
- /* channel 3 */ \
- (*((volatile Word *) io_p2v (_DDAR3)))
-#define SetDCSR3 /* Set DMA Control & Status Reg. */ \
- /* channel 3 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR3)))
-#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
- /* channel 3 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR3)))
-#define RdDCSR3 /* Read DMA Control & Status Reg. */ \
- /* channel 3 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR3)))
-#define DBSA3 /* DMA Buffer Start address reg. A */ \
- /* channel 3 */ \
- (*((volatile Address *) io_p2v (_DBSA3)))
-#define DBTA3 /* DMA Buffer Transfer count */ \
- /* reg. A channel 3 */ \
- (*((volatile Word *) io_p2v (_DBTA3)))
-#define DBSB3 /* DMA Buffer Start address reg. B */ \
- /* channel 3 */ \
- (*((volatile Address *) io_p2v (_DBSB3)))
-#define DBTB3 /* DMA Buffer Transfer count */ \
- /* reg. B channel 3 */ \
- (*((volatile Word *) io_p2v (_DBTB3)))
-
-#define DDAR4 /* DMA Device Address Reg. */ \
- /* channel 4 */ \
- (*((volatile Word *) io_p2v (_DDAR4)))
-#define SetDCSR4 /* Set DMA Control & Status Reg. */ \
- /* channel 4 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR4)))
-#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
- /* channel 4 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR4)))
-#define RdDCSR4 /* Read DMA Control & Status Reg. */ \
- /* channel 4 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR4)))
-#define DBSA4 /* DMA Buffer Start address reg. A */ \
- /* channel 4 */ \
- (*((volatile Address *) io_p2v (_DBSA4)))
-#define DBTA4 /* DMA Buffer Transfer count */ \
- /* reg. A channel 4 */ \
- (*((volatile Word *) io_p2v (_DBTA4)))
-#define DBSB4 /* DMA Buffer Start address reg. B */ \
- /* channel 4 */ \
- (*((volatile Address *) io_p2v (_DBSB4)))
-#define DBTB4 /* DMA Buffer Transfer count */ \
- /* reg. B channel 4 */ \
- (*((volatile Word *) io_p2v (_DBTB4)))
-
-#define DDAR5 /* DMA Device Address Reg. */ \
- /* channel 5 */ \
- (*((volatile Word *) io_p2v (_DDAR5)))
-#define SetDCSR5 /* Set DMA Control & Status Reg. */ \
- /* channel 5 (write) */ \
- (*((volatile Word *) io_p2v (_SetDCSR5)))
-#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
- /* channel 5 (write) */ \
- (*((volatile Word *) io_p2v (_ClrDCSR5)))
-#define RdDCSR5 /* Read DMA Control & Status Reg. */ \
- /* channel 5 (read) */ \
- (*((volatile Word *) io_p2v (_RdDCSR5)))
-#define DBSA5 /* DMA Buffer Start address reg. A */ \
- /* channel 5 */ \
- (*((volatile Address *) io_p2v (_DBSA5)))
-#define DBTA5 /* DMA Buffer Transfer count */ \
- /* reg. A channel 5 */ \
- (*((volatile Word *) io_p2v (_DBTA5)))
-#define DBSB5 /* DMA Buffer Start address reg. B */ \
- /* channel 5 */ \
- (*((volatile Address *) io_p2v (_DBSB5)))
-#define DBTB5 /* DMA Buffer Transfer count */ \
- /* reg. B channel 5 */ \
- (*((volatile Word *) io_p2v (_DBTB5)))
+#define DDAR0 /* DMA Device Address Reg. */ \
+ /* channel 0 */ \
+ (*((volatile Word *) io_p2v (_DDAR0)))
+#define SetDCSR0 /* Set DMA Control & Status Reg. */ \
+ /* channel 0 (write) */ \
+ (*((volatile Word *) io_p2v (_SetDCSR0)))
+#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
+ /* channel 0 (write) */ \
+ (*((volatile Word *) io_p2v (_ClrDCSR0)))
+#define RdDCSR0 /* Read DMA Control & Status Reg. */ \
+ /* channel 0 (read) */ \
+ (*((volatile Word *) io_p2v (_RdDCSR0)))
+#define DBSA0 /* DMA Buffer Start address reg. A */ \
+ /* channel 0 */ \
+ (*((volatile Address *) io_p2v (_DBSA0)))
+#define DBTA0 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 0 */ \
+ (*((volatile Word *) io_p2v (_DBTA0)))
+#define DBSB0 /* DMA Buffer Start address reg. B */ \
+ /* channel 0 */ \
+ (*((volatile Address *) io_p2v (_DBSB0)))
+#define DBTB0 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 0 */ \
+ (*((volatile Word *) io_p2v (_DBTB0)))
+
+#define DDAR1 /* DMA Device Address Reg. */ \
+ /* channel 1 */ \
+ (*((volatile Word *) io_p2v (_DDAR1)))
+#define SetDCSR1 /* Set DMA Control & Status Reg. */ \
+ /* channel 1 (write) */ \
+ (*((volatile Word *) io_p2v (_SetDCSR1)))
+#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
+ /* channel 1 (write) */ \
+ (*((volatile Word *) io_p2v (_ClrDCSR1)))
+#define RdDCSR1 /* Read DMA Control & Status Reg. */ \
+ /* channel 1 (read) */ \
+ (*((volatile Word *) io_p2v (_RdDCSR1)))
+#define DBSA1 /* DMA Buffer Start address reg. A */ \
+ /* channel 1 */ \
+ (*((volatile Address *) io_p2v (_DBSA1)))
+#define DBTA1 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 1 */ \
+ (*((volatile Word *) io_p2v (_DBTA1)))
+#define DBSB1 /* DMA Buffer Start address reg. B */ \
+ /* channel 1 */ \
+ (*((volatile Address *) io_p2v (_DBSB1)))
+#define DBTB1 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 1 */ \
+ (*((volatile Word *) io_p2v (_DBTB1)))
+
+#define DDAR2 /* DMA Device Address Reg. */ \
+ /* channel 2 */ \
+ (*((volatile Word *) io_p2v (_DDAR2)))
+#define SetDCSR2 /* Set DMA Control & Status Reg. */ \
+ /* channel 2 (write) */ \
+ (*((volatile Word *) io_p2v (_SetDCSR2)))
+#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
+ /* channel 2 (write) */ \
+ (*((volatile Word *) io_p2v (_ClrDCSR2)))
+#define RdDCSR2 /* Read DMA Control & Status Reg. */ \
+ /* channel 2 (read) */ \
+ (*((volatile Word *) io_p2v (_RdDCSR2)))
+#define DBSA2 /* DMA Buffer Start address reg. A */ \
+ /* channel 2 */ \
+ (*((volatile Address *) io_p2v (_DBSA2)))
+#define DBTA2 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 2 */ \
+ (*((volatile Word *) io_p2v (_DBTA2)))
+#define DBSB2 /* DMA Buffer Start address reg. B */ \
+ /* channel 2 */ \
+ (*((volatile Address *) io_p2v (_DBSB2)))
+#define DBTB2 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 2 */ \
+ (*((volatile Word *) io_p2v (_DBTB2)))
+
+#define DDAR3 /* DMA Device Address Reg. */ \
+ /* channel 3 */ \
+ (*((volatile Word *) io_p2v (_DDAR3)))
+#define SetDCSR3 /* Set DMA Control & Status Reg. */ \
+ /* channel 3 (write) */ \
+ (*((volatile Word *) io_p2v (_SetDCSR3)))
+#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
+ /* channel 3 (write) */ \
+ (*((volatile Word *) io_p2v (_ClrDCSR3)))
+#define RdDCSR3 /* Read DMA Control & Status Reg. */ \
+ /* channel 3 (read) */ \
+ (*((volatile Word *) io_p2v (_RdDCSR3)))
+#define DBSA3 /* DMA Buffer Start address reg. A */ \
+ /* channel 3 */ \
+ (*((volatile Address *) io_p2v (_DBSA3)))
+#define DBTA3 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 3 */ \
+ (*((volatile Word *) io_p2v (_DBTA3)))
+#define DBSB3 /* DMA Buffer Start address reg. B */ \
+ /* channel 3 */ \
+ (*((volatile Address *) io_p2v (_DBSB3)))
+#define DBTB3 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 3 */ \
+ (*((volatile Word *) io_p2v (_DBTB3)))
+
+#define DDAR4 /* DMA Device Address Reg. */ \
+ /* channel 4 */ \
+ (*((volatile Word *) io_p2v (_DDAR4)))
+#define SetDCSR4 /* Set DMA Control & Status Reg. */ \
+ /* channel 4 (write) */ \
+ (*((volatile Word *) io_p2v (_SetDCSR4)))
+#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
+ /* channel 4 (write) */ \
+ (*((volatile Word *) io_p2v (_ClrDCSR4)))
+#define RdDCSR4 /* Read DMA Control & Status Reg. */ \
+ /* channel 4 (read) */ \
+ (*((volatile Word *) io_p2v (_RdDCSR4)))
+#define DBSA4 /* DMA Buffer Start address reg. A */ \
+ /* channel 4 */ \
+ (*((volatile Address *) io_p2v (_DBSA4)))
+#define DBTA4 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 4 */ \
+ (*((volatile Word *) io_p2v (_DBTA4)))
+#define DBSB4 /* DMA Buffer Start address reg. B */ \
+ /* channel 4 */ \
+ (*((volatile Address *) io_p2v (_DBSB4)))
+#define DBTB4 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 4 */ \
+ (*((volatile Word *) io_p2v (_DBTB4)))
+
+#define DDAR5 /* DMA Device Address Reg. */ \
+ /* channel 5 */ \
+ (*((volatile Word *) io_p2v (_DDAR5)))
+#define SetDCSR5 /* Set DMA Control & Status Reg. */ \
+ /* channel 5 (write) */ \
+ (*((volatile Word *) io_p2v (_SetDCSR5)))
+#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
+ /* channel 5 (write) */ \
+ (*((volatile Word *) io_p2v (_ClrDCSR5)))
+#define RdDCSR5 /* Read DMA Control & Status Reg. */ \
+ /* channel 5 (read) */ \
+ (*((volatile Word *) io_p2v (_RdDCSR5)))
+#define DBSA5 /* DMA Buffer Start address reg. A */ \
+ /* channel 5 */ \
+ (*((volatile Address *) io_p2v (_DBSA5)))
+#define DBTA5 /* DMA Buffer Transfer count */ \
+ /* reg. A channel 5 */ \
+ (*((volatile Word *) io_p2v (_DBTA5)))
+#define DBSB5 /* DMA Buffer Start address reg. B */ \
+ /* channel 5 */ \
+ (*((volatile Address *) io_p2v (_DBSB5)))
+#define DBTB5 /* DMA Buffer Transfer count */ \
+ /* reg. B channel 5 */ \
+ (*((volatile Word *) io_p2v (_DBTB5)))