-
-typedef struct qmx83xx {
- u32 cmxgcr; /* CMX general clock route register */
- u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
- u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
- u32 cmxsi1syr; /* CMX SI1 SYNC route register */
- u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
- u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
- u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
- u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
- u32 cmxupcr; /* CMX UPC clock route register */
- u8 res0[0x1C];
-} qmx83xx_t;
-
-/*
-* QE Timers
-*/
-
-typedef struct qet83xx {
- u8 gtcfr1; /* Timer 1 and Timer 2 global configuration register */
- u8 res0[0x3];
- u8 gtcfr2; /* Timer 3 and timer 4 global configuration register */
- u8 res1[0xB];
- u16 gtmdr1; /* Timer 1 mode register */
- u16 gtmdr2; /* Timer 2 mode register */
- u16 gtrfr1; /* Timer 1 reference register */
- u16 gtrfr2; /* Timer 2 reference register */
- u16 gtcpr1; /* Timer 1 capture register */
- u16 gtcpr2; /* Timer 2 capture register */
- u16 gtcnr1; /* Timer 1 counter */
- u16 gtcnr2; /* Timer 2 counter */
- u16 gtmdr3; /* Timer 3 mode register */
- u16 gtmdr4; /* Timer 4 mode register */
- u16 gtrfr3; /* Timer 3 reference register */
- u16 gtrfr4; /* Timer 4 reference register */
- u16 gtcpr3; /* Timer 3 capture register */
- u16 gtcpr4; /* Timer 4 capture register */
- u16 gtcnr3; /* Timer 3 counter */
- u16 gtcnr4; /* Timer 4 counter */
- u16 gtevr1; /* Timer 1 event register */
- u16 gtevr2; /* Timer 2 event register */
- u16 gtevr3; /* Timer 3 event register */
- u16 gtevr4; /* Timer 4 event register */
- u16 gtps; /* Timer 1 prescale register */
- u8 res2[0x46];
-} qet83xx_t;
-
-/*
-* spi
-*/
-
-typedef struct spi83xx {
- u8 res0[0x20];
- u32 spmode; /* SPI mode register */
- u8 res1[0x2];
- u8 spie; /* SPI event register */
- u8 res2[0x1];
- u8 res3[0x2];
- u8 spim; /* SPI mask register */
- u8 res4[0x1];
- u8 res5[0x1];
- u8 spcom; /* SPI command register */
- u8 res6[0x2];
- u32 spitd; /* SPI transmit data register (cpu mode) */
- u32 spird; /* SPI receive data register (cpu mode) */
- u8 res7[0x8];
-} spi83xx_t;
-
-/*
-* mcc
-*/
-
-typedef struct mcc83xx {
- u32 mcce; /* MCC event register */
- u32 mccm; /* MCC mask register */
- u32 mccf; /* MCC configuration register */
- u32 merl; /* MCC emergency request level register */
- u8 res0[0xF0];
-} mcc83xx_t;
-
-/*
-* brg
-*/
-
-typedef struct brg83xx {
- u32 brgc1; /* BRG1 configuration register */
- u32 brgc2; /* BRG2 configuration register */
- u32 brgc3; /* BRG3 configuration register */
- u32 brgc4; /* BRG4 configuration register */
- u32 brgc5; /* BRG5 configuration register */
- u32 brgc6; /* BRG6 configuration register */
- u32 brgc7; /* BRG7 configuration register */
- u32 brgc8; /* BRG8 configuration register */
- u32 brgc9; /* BRG9 configuration register */
- u32 brgc10; /* BRG10 configuration register */
- u32 brgc11; /* BRG11 configuration register */
- u32 brgc12; /* BRG12 configuration register */
- u32 brgc13; /* BRG13 configuration register */
- u32 brgc14; /* BRG14 configuration register */
- u32 brgc15; /* BRG15 configuration register */
- u32 brgc16; /* BRG16 configuration register */
- u8 res0[0x40];
-} brg83xx_t;
-
-/*
-* USB
-*/
-
-typedef struct usb83xx {
- u8 usmod; /* USB mode register */
- u8 usadd; /* USB address register */
- u8 uscom; /* USB command register */
- u8 res0[0x1];
- u16 usep0; /* USB endpoint register 0 */
- u16 usep1; /* USB endpoint register 1 */
- u16 usep2; /* USB endpoint register 2 */
- u16 usep3; /* USB endpoint register 3 */
- u8 res1[0x4];
- u16 usber; /* USB event register */
- u8 res2[0x2];
- u16 usbmr; /* USB mask register */
- u8 res3[0x1];
- u8 usbs; /* USB status register */
- u32 ussft; /* USB start of frame timer */
- u8 res4[0x24];
-} usb83xx_t;
-
-/*
-* SI
-*/
-
-typedef struct si1_83xx {
- u16 siamr1; /* SI1 TDMA mode register */
- u16 sibmr1; /* SI1 TDMB mode register */
- u16 sicmr1; /* SI1 TDMC mode register */
- u16 sidmr1; /* SI1 TDMD mode register */
- u8 siglmr1_h; /* SI1 global mode register high */
- u8 res0[0x1];
- u8 sicmdr1_h; /* SI1 command register high */
- u8 res2[0x1];
- u8 sistr1_h; /* SI1 status register high */
- u8 res3[0x1];
- u16 sirsr1_h; /* SI1 RAM shadow address register high */
- u8 sitarc1; /* SI1 RAM counter Tx TDMA */
- u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
- u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
- u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
- u8 sirarc1; /* SI1 RAM counter Rx TDMA */
- u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
- u8 sircrc1; /* SI1 RAM counter Rx TDMC */
- u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
- u8 res4[0x8];
- u16 siemr1; /* SI1 TDME mode register 16 bits */
- u16 sifmr1; /* SI1 TDMF mode register 16 bits */
- u16 sigmr1; /* SI1 TDMG mode register 16 bits */
- u16 sihmr1; /* SI1 TDMH mode register 16 bits */
- u8 siglmg1_l; /* SI1 global mode register low 8 bits */
- u8 res5[0x1];
- u8 sicmdr1_l; /* SI1 command register low 8 bits */
- u8 res6[0x1];
- u8 sistr1_l; /* SI1 status register low 8 bits */
- u8 res7[0x1];
- u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
- u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
- u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
- u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
- u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
- u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
- u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
- u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
- u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
- u8 res8[0x8];
- u32 siml1; /* SI1 multiframe limit register */
- u8 siedm1; /* SI1 extended diagnostic mode register */
- u8 res9[0xBB];
-} si1_83xx_t;