+#define CFG_MPC85xx_GUTS_OFFSET (0xE0000)
+#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
+#define CFG_MPC85xx_ECM_OFFSET (0x0000)
+#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
+#define CFG_MPC85xx_DDR_OFFSET (0x2000)
+#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
+#define CFG_MPC85xx_DDR2_OFFSET (0x6000)
+#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET)
+#define CFG_MPC85xx_LBC_OFFSET (0x5000)
+#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
+#define CFG_MPC85xx_PCIX_OFFSET (0x8000)
+#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
+#define CFG_MPC85xx_PCIX2_OFFSET (0x9000)
+#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
+#define CFG_MPC85xx_L2_OFFSET (0x20000)
+#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
+#define CFG_MPC85xx_DMA_OFFSET (0x21000)
+#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
+#define CFG_MPC85xx_PIC_OFFSET (0x40000)
+#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
+#define CFG_MPC85xx_CPM_OFFSET (0x80000)
+#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)