- uint init_address; /* 0x2148 - DDR training initialization address */
- uint init_ext_address; /* 0x214C - DDR training initialization extended address */
- char res8_1[2728];
+ uint init_addr; /* 0x2148 - DDR training initialization address */
+ uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
+ char res8_1[16];
+ uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
+ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
+ char reg8_1a[8];
+ uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
+ uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
+ uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/
+ uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
+ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
+ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
+ char res8_1b[2672];