- uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
- char res26[4];
- uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
- char res27[44];
- uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
- uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
- uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
- uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
- char res28[16];
- uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
- uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
- uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
- char res29[3476];
+ uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
+ char res26[4];
+ uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
+ char res27[44];
+ uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
+ uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
+ uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
+ uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
+ char res28[16];
+ uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
+ uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
+ uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
+ char res29[3476];
- u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */
-#define MPC86xx_I2CADR_MASK 0xFE
- char res1[3];
- u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */
-#define MPC86xx_I2CFDR_MASK 0x3F
- char res2[3];
- u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */
-#define MPC86xx_I2CCR_MEN 0x80
-#define MPC86xx_I2CCR_MIEN 0x40
-#define MPC86xx_I2CCR_MSTA 0x20
-#define MPC86xx_I2CCR_MTX 0x10
-#define MPC86xx_I2CCR_TXAK 0x08
-#define MPC86xx_I2CCR_RSTA 0x04
-#define MPC86xx_I2CCR_BCST 0x01
- char res3[3];
- u_char i2csr1; /* 0x300c - I2C 1 Status Register */
-#define MPC86xx_I2CSR_MCF 0x80
-#define MPC86xx_I2CSR_MAAS 0x40
-#define MPC86xx_I2CSR_MBB 0x20
-#define MPC86xx_I2CSR_MAL 0x10
-#define MPC86xx_I2CSR_BCSTM 0x08
-#define MPC86xx_I2CSR_SRW 0x04
-#define MPC86xx_I2CSR_MIF 0x02
-#define MPC86xx_I2CSR_RXAK 0x01
- char res4[3];
- u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */
-#define MPC86xx_I2CDR_DATA 0xFF
- char res5[3];
- u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */
-#define MPC86xx_I2CDFSRR 0x3F
- char res6[235];
-
- u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */
- char res7[3];
- u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */
- char res8[3];
- u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */
- char res9[3];
- u_char i2csr2; /* 0x310c - I2C 2 Status Register */
- char res10[3];
- u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */
- char res11[3];
- u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */
- char res12[3819];
+ struct fsl_i2c i2c[2];
+ u8 res[4096 - 2 * sizeof(struct fsl_i2c)];
- uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
- char res3[12];
- uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
- char res4[4];
- uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
- char res5[4];
- uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
- char res6[12];
- uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
- char res7[4];
- uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
- char res8[4];
- uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
- char res9[12];
- uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
- char res10[4];
- uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
- char res11[4];
- uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
- char res12[12];
- uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
- char res13[4];
- uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
- char res14[4];
- uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
- char res15[236];
- uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
- char res16[4];
- uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
- char res17[4];
- uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
- char res18[12];
- uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
- char res19[4];
- uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
- char res20[4];
- uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
- char res21[12];
- uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
- char res22[4];
- uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
- char res23[4];
- uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
- char res24[12];
- uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
- char res25[4];
- uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
- char res26[4];
- uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
- char res27[12];
- uint hedr; /* 0xae00 - HT Error Detect register */
- char res28[4];
- uint heier; /* 0xae08 - HT Error Interrupt Enable register */
- char res29[4];
- uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
- char res30[12];
- uint hecsr; /* 0xae20 - HT Error Capture Status register */
- char res31[4];
- uint hec0; /* 0xae28 - HT Error Capture 0 register */
- uint hec1; /* 0xae2c - HT Error Capture 1 register */
- uint hec2; /* 0xae30 - HT Error Capture 2 register */
- char res32[460];
+ uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
+ char res3[12];
+ uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
+ char res4[4];
+ uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
+ char res5[4];
+ uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
+ char res6[12];
+ uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
+ char res7[4];
+ uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
+ char res8[4];
+ uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
+ char res9[12];
+ uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
+ char res10[4];
+ uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
+ char res11[4];
+ uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
+ char res12[12];
+ uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
+ char res13[4];
+ uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
+ char res14[4];
+ uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
+ char res15[236];
+ uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
+ char res16[4];
+ uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
+ char res17[4];
+ uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
+ char res18[12];
+ uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
+ char res19[4];
+ uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
+ char res20[4];
+ uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
+ char res21[12];
+ uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
+ char res22[4];
+ uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
+ char res23[4];
+ uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
+ char res24[12];
+ uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
+ char res25[4];
+ uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
+ char res26[4];
+ uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
+ char res27[12];
+ uint hedr; /* 0xae00 - HT Error Detect register */
+ char res28[4];
+ uint heier; /* 0xae08 - HT Error Interrupt Enable register */
+ char res29[4];
+ uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
+ char res30[12];
+ uint hecsr; /* 0xae20 - HT Error Capture Status register */
+ char res31[4];
+ uint hec0; /* 0xae28 - HT Error Capture 0 register */
+ uint hec1; /* 0xae2c - HT Error Capture 1 register */
+ uint hec2; /* 0xae30 - HT Error Capture 2 register */
+ char res32[460];
- uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
- uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
- char res8[52];
- uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
- char res9[4];
- uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
- char res10[4];
- uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
- char res11[4];
- uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
- char res12[4];
- uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
- char res13[4];
- uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
- char res14[4];
- uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
- char res15[4];
- uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
- char res16[4];
- uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
- char res17[64];
+ uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
+ uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
+ char res8[52];
+ uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
+ char res9[4];
+ uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
+ char res10[4];
+ uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
+ char res11[4];
+ uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
+ char res12[4];
+ uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
+ char res13[4];
+ uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
+ char res14[4];
+ uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
+ char res15[4];
+ uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
+ char res16[4];
+ uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
+ char res17[64];
- char res18[4];
- uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
- char res19[4];
- uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
- char res20[4];
- uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
- char res21[4];
- uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
- char res22[4];
- uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
- char res23[4];
- uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
- char res24[4];
- uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
- char res25[192];
+ char res18[4];
+ uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
+ char res19[4];
+ uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
+ char res20[4];
+ uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
+ char res21[4];
+ uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
+ char res22[4];
+ uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
+ char res23[4];
+ uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
+ char res24[4];
+ uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
+ char res25[192];
- uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
- char res29[4];
- uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
- char res30[4];
- uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
- char res31[4];
- uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
- char res32[4];
- uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
- char res33[4];
- uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
- char res34[4];
- uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
- char res35[4];
- uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
- char res36[4];
- uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
- char res37[64];
+ uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
+ char res29[4];
+ uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
+ char res30[4];
+ uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
+ char res31[4];
+ uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
+ char res32[4];
+ uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
+ char res33[4];
+ uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
+ char res34[4];
+ uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
+ char res35[4];
+ uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
+ char res36[4];
+ uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
+ char res37[64];
- uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
- uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
- uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
- uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
- uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
- uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
- uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
- uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
- uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
- uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
- uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
- uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
- uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
- uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
- uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
- uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
- uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
- uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
- uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
- uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
- uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
- uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
- uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
- uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
- uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
- uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
- uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
- uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
- uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
- uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
+ uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
+ uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
+ uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
+ uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
+ uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
+ uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
+ uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
+ uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
+ uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
+ uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
+ uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
+ uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
+ uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
+ uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
+ uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
+ uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
+ uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
+ uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
+ uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
+ uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
+ uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
+ uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
+ uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
+ uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
+ uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
+ uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
+ uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
+ uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
+ uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
+ uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */